System and method for the aggregation of 10GBASE-R signals into pseudo 100GBASE-R signals
View Patent ↗An Ethernet physical layer (PHY) module is provided with a method for transceiving between a 10GBASE-R client interface and a 100G attachment interface. On each of ten client interface logical lanes a 10GBASE-R signal is accepted. Each 10GBASE-R logical lane is demultiplexed into two 5 gigabit per second (Gbps) pseudo 100GBASE-R logical lanes, creating a total of twenty pseudo 100GBASE-R logical lanes. The pseudo 100GBASE-R logical lanes are arranged into n groups of 20/n pseudo 100GBASE-R logical lanes. Further, the pseudo 100GBASE-R logical lanes from each group are arranged into a 100G attachment logical lane. Finally, a 100G attachment logical lane is transmitted at an attachment interface on each of n physical lanes. In the reverse direction, each of n physical lanes accepts a 100G attachment logical lane at the attachment interface, and a de-aggregation process supplies a 10GBASE-R signal on each of ten client interface logical lanes.
1. In an Ethernet physical layer (PHY) module, a method for transceiving between a 10GBASE-R client interface and a 100G attachment interface, the method comprising:
on each of ten client interface logical lanes, accepting a 10GBASE-R signal;
demultiplexing each 10GBASE-R logical lane into two 5 gigabit per second (Gbps) pseudo 100GBASE-R logical lanes, creating a total of twenty pseudo 100GBASE-R logical lanes;
arranging the twenty pseudo 100GBASE-R logical lanes into n groups of 20/n pseudo 100GBASE-R logical lanes;
arranging the pseudo 100GBASE-R logical lanes from each group into a 100G attachment logical lane; and,
on each of n physical lanes, transmitting a 100G attachment logical lane at an attachment interface.
2. The method of claim 1 wherein arranging the pseudo 100GBASE-R logical lanes from each group into a 100G attachment logical lane includes interleaving the 20/n pseudo 100GBASE-R logical lanes from each group into a 100G attachment logical lane.
3. The method of claim 1 further comprising:
on each of n physical lanes, accepting a 100G attachment logical lane at the attachment interface;
deinterleaving each 100G attachment logical lane into a group of 20/n pseudo 100GBASE-R logical lanes;
arranging the n groups of 20/n pseudo 100GBASE-R logical lanes into ten sets, where each set includes two pseudo 100GBASE-R logical lanes;
multiplexing the two pseudo 100GBASE-R logical lanes in each set into a 10GBASE-R logical lane, creating a total of ten 10GBASE-R logical lanes; and,
on each of ten client interface logical lanes, transmitting a 10GBASE-R signal.
4. The method of claim 2 wherein interleaving the 20/n pseudo 100GBASE-R logical lanes from each group into the 100G attachment logical lane includes interleaving the pseudo 100GBASE-R logical lanes into an interface selected from a group consisting of a 100 Gbps (gigabit per second) 10×10G Attachment Unit Interface (CAUI-10) interface, a 100 Gbps 4×25G Attachment Unit Interface (CAUI-4) interface, a 100 Gbps CPPI-N interface where N is selected from a group, consisting of 1, 2, 4, 5, and 10, and a 100GBASE-<a>R<b>, where <a> represents the interface type and <b> represents the number of physical lanes.
5. The method of claim 1 wherein arranging the twenty pseudo 100GBASE-R logical lanes into n groups includes n being equal to a value selected from a group consisting of 1, 2, 4, 5, and 10.
6. The method of claim 3 wherein arranging each 100G attachment logical lane into the group of 20/n pseudo 100GBASE-R logical lanes includes n being equal to a value selected from a group consisting of 1, 2, 4, 5, and 10.
7. The method of claim 1 further comprising:
subsequent to accepting the 10GBASE-R signals at the client interface, synchronizing the 10GBASE-R signals.
8. The method of claim 7 wherein synchronizing the 10GBASE-R signals comprises:
descrambling 10GBASE-R 64B/66B blocks;
modifying a quantity of 10GBASE-R 64B/66B blocks to adapt data rates; and,
re-scrambling the 10GBASE-R 64B/66B blocks.
9. The method of claim 7 wherein synchronizing the 10GBASE-R signals comprises:
decoding 10GBASE-R 64B/66B blocks into XGMII signals;
modifying a quantity of XGMII groups to adapt data rates; and,
encoding the XGMII groups into 10GBASE-R 64B/66B blocks.
10. The method of claim 3 further comprising:
subsequent to arranging the twenty pseudo 100GBASE-R logical lanes into n groups of 20/n pseudo 100GBASE-R logical lanes, crosspoint switching the twenty pseudo 100GBASE-R logical lanes.
11. The method of claim 1 wherein accepting the 10GBASE-R signal on each of ten client interface logical lanes includes each client interface logical lane being associated with a corresponding physical lane.
12. An Ethernet physical layer (PHY) module with a system for transceiving between a 10GBASE-R client interface and a 100G attachment interface, the system comprising:
an aggregator having a client interface of ten logical lanes, each logical lane accepting a 10GBASE-R signal, the aggregator demultiplexing each 10GBASE-R logical lane into two 5 gigabit per second (Gbps) pseudo 100GBASE-R logical lanes, creating a total of twenty pseudo 100GBASE-R logical lanes, the aggregator arranging the twenty pseudo 100GBASE-R logical lanes into n groups of 20/n pseudo 100G-BASE-R logical lanes, and arranging the pseudo 100GBASE-R logical lanes from each group into a 100G attachment logical lane, the aggregator having an attachment interface to transmit a 100G attachment logical lane on each of n physical lanes.
13. The system of claim 12 wherein the aggregator interleaves the 20/n pseudo 100GBASE-R logical lanes from each group into a 100G attachment logical lane.
14. The system of claim 12 further comprising:
a de-aggregator having an attachment interface to accept a 100G attachment logical lane on each of n physical lanes, the de-aggregator deinterleaving each 100G attachment logical lane into a group of 20/n pseudo 100GBASE-R logical lanes, and arranging the n groups of 20/n pseudo 100GBASE-R logical lanes into ten sets, where each set includes two pseudo 100GBASE-R logical lanes, the de-aggregator multiplexing the two pseudo 100GBASE-R logical lanes in each set into a 10GBASE-R logical lane, creating a total of ten 10GBASE-R logical lanes, and transmitting each 10GBASE-R signal via a logical lane at a client interface.
15. The system of claim 13 wherein the aggregator interleaves the 20/n pseudo 100GBASE-R logical lanes from each group into an interface selected from a group consisting of a 100 Gbps (gigabit per second) 10×10G Attachment Unit Interface (CAUI-100) interface, a 100 Gbps 4×250 Attachment Unit Interface (CAUI-4) interface, a 100 Gbps CPPI-N interface where N is selected from a group consisting of 1, 2, 4, 5, and 10, and a 100GBASE-<a>R<b>, where <a> represents the interface type and <b> represents the number of physical lanes.
16. The system of claim 12 wherein the aggregator arranges the twenty pseudo 100GBASE-R logical lanes into n groups, where n is equal to a value selected from a group consisting of 1, 2, 4, 5, and 10.
17. The system of claim 14 wherein the de-aggregator arranges each 100G attachment logical lane into the group of 20/n pseudo 100GBASE-R logical lanes, where n is equal to a value selected from a group consisting of 1, 2, 4, 5, and 10.
18. The system of claim 12 wherein the aggregator, subsequent to accepting the 10GBASE-R signals at the client interface, synchronizes the 10GBASE-R signals.
19. The system of claim 18 wherein the aggregator synchronizes the 10GBASE-R signals by descrambling 10GBASE-R 64B/66B blocks, modifying a quantity of 10GBASE-R 64B/66B blocks to adapt data rates, and re-scrambling the 10GBASE-R 64B/66B blocks.
20. The system of claim 18 wherein the aggregator synchronizes the 10GBASE-R signals by decoding 10GBASE-R 64B/66B blocks into XGMII signals, modifying a quantity of XGMII groups to adapt data rates, and encoding the XGMII groups into 10GBASE-R 64B/66B blocks.
21. The system of claim 14 wherein the aggregator, subsequent to arranging the twenty pseudo 100GBASE-R logical lanes into n groups of 20/n pseudo 100GBASE-R logical lanes, crosspoint switches the twenty pseudo 100GBASE-R logical lanes; and,
wherein the de-aggregator, subsequent to arranging the n groups of 20/n pseudo 100GBASE-R logical lanes into ten sets, crosspoint switches the twenty pseudo 100GBASE-R logical lanes.
22. The system of claim 12 wherein the aggregator client interface has a physical lane associated with each logical lane.
23. An Ethernet physical layer (PHY) module with a system for transceiving between a 10GBASE-R client interface and a 100G attachment interface, the system comprising:
a de-aggregator having an attachment interface to accept a 100G attachment logical lane on each of n physical lanes, the de-aggregator deinterleaving each 10G attachment logical lane into a group of 20/n pseudo 100GBASE-R logical lanes, and arranging the n groups of 20/n pseudo 100GBASE-R logical lanes into ten sets, where each set includes two pseudo 100GBASE-R logical lanes, the de-aggregator multiplexing the two pseudo 100GBASE-R logical lanes in each set into a 10GBASE-R logical lane, creating a total of ten 10GBASE-R logical lanes, and transmitting each 10GBASE-R signal via a logical lane at a client interface.