Systems and methods facilitating reduced latency via stashing in system on chips
View Patent ↗Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.
1. A method, comprising:
stashing, by a device comprising a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the first cache memory being a shared cache memory for a plurality of processors and the plurality of cache memories being associated with a multi-level cache memory architecture;
stashing second data, representative of an address to the first data in the first cache memory, in a second cache memory of the plurality of cache memories, the second cache memory being associated with a processor of the plurality of processors;
generating control information comprising a first instruction to cause monitoring contents of the second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and
prefetching the first data from the first cache memory to the second cache memory based on execution of the first instruction.
2. The method of claim 1 , wherein the prefetching and the generating are performed concurrently.
3. The method of claim 1 , wherein the defined condition comprises the second cache memory failing to store the first data associated with the address.
4. The method of claim 1 , wherein the first cache memory is a shared cache memory for two or more of the plurality of multi-processor CPU cores.
5. The method of claim 1 , wherein the first cache memory is an L2 shared cache memory and the second cache memory is an L1 per processor cache memory.
6. The method of claim 1 , wherein a defined address associated with the first data is also stashed into the first cache memory and the second cache memory.
7. A method, comprising:
stashing, by a device comprising a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the first cache memory being a shared cache memory for a plurality of processors and the plurality of cache memories being associated with a multi-level cache memory architecture;
stashing second data comprising a first address to the first data in a second cache memory of the plurality of processors, wherein the second cache memory is part of a per processor memory cache associated with a processor of the plurality of processors;
determining that the first data will be executed on the processor of the plurality of processors, the determining being based on a detected request for a cache line associated with the second data; and
generating control information comprising a first instruction to cause prefetching the first data at the first address into the second cache memory of the plurality of cache memories.
8. The method of claim 7 , further comprising: detecting the request for the first address.
9. The method of claim 7 , wherein the generating is performed in response to the determining.
10. The method of claim 7 , wherein the first instruction also causes prefetching second data into the second cache memory, wherein the second data is associated with a set of addresses relative to the first address.
11. The method of claim 10 , wherein the set of addresses is located at a first location and the first address is located at a second location, wherein the first location is subsequent to the second location.
12. The method of claim 10 , wherein the set of addresses is located at a first location and the first address is located at a second location, wherein the first location is subsequent to the second location in sequential order.
13. A system on chip, comprising:
a plurality of cache memories communicatively coupled to a plurality of multi-processor central processing unit cores, the plurality of cache memories being associated with a multi-level cache memory architecture and comprising a first cache memory that is a shared memory accessible by the plurality of multiprocessor central processing unit cores, and a second cache memory accessible by a single processor core of the plurality of multiprocessor central processing unit cores;
a cache memory control circuit configured to generate a signal to cause first data and a first address for the first data to be stashed into the first cache memory of a plurality of cache memories and the first address for the first data to be stashed into the second cache memory; and
a device configured to perform operations comprising:
fetching data for the first address associated with the first data to be executed on the single processor core, the fetching being in response to a determination that the single processor core has requested the first address in the second cache memory; and
prefetching a set of addresses relative to the first address, the prefetching being performed in response to initiation of the fetching.
14. The system on chip of claim 13 , wherein the fetching and the prefetching are performed concurrently.
15. The system on chip of claim 13 , wherein the set of addresses comprise instructions to be executed on the defined multi-processor central processing unit core.
16. The system on chip of claim 13 , wherein the second cache memory is a per processor cache memory for one of the plurality of multi-processor cache memories.
17. The method of claim 1 , wherein the defined condition is the processor accessing a cache line associated with the address.
18. The method of claim 1 , wherein the first cache memory is an L3 shared cache memory and the second cache memory is an L2 per processor cache memory.
19. The system on a chip of claim 13 , wherein the single processor core accesses a cache line associated with the first address in the second cache memory.