IP Library Granted Patent US 8,650,464
Granted Patent B1
US 8,650,464 · App. 13/225,337 · Granted Feb 11, 2014

Symmetric diagonal interleaving and encoding/decoding circuit and method

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Quick Facts
Patent No.
US 8,650,464
App. No.
13/225,337
Granted
Feb 11, 2014
Kind
B1
Abstract

A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with a different codeword in a different group.

Claims (72)

1. A method of decoding comprising:

receiving a current sequence of bits from a communication network;

checking for errors in a plurality of codewords grouped into multiple groups;

wherein each codeword has a first set of said bits comprised within the current sequence and a second set of said bits comprised in a plurality of past sequences that are received from the communication network prior to receipt of the current sequence;

wherein each codeword in a group has no bit in common with another codeword in said group;

wherein each codeword in said group has a bit in common with another codeword in another group;

wherein the first set and the second set together comprise message bits and parity bits of said each codeword; and

storing in memory, a result obtained at least partially based on said checking.

2. The method of claim 1 wherein:

the communication network comprises an optical network;

the sequences are comprised in frames obtained by demodulating a signal of light received from the optical network; and

each row of a frame among said frames comprises a sequence among said sequences.

3. The method of claim 1 wherein:

the first set of said each codeword has multiple bits in common with second sets of codewords received later from the communication network.

4. The method of claim 1 wherein:

said parity bits are comprised in said first set of said each codeword.

5. The method of claim 1 wherein:

the parity bits are located in a group of columns central to a two-dimensional array used to access said bits in said current sequence;

the group of columns are sandwiched in said array, between two groups of outermost columns thereof comprising the message bits.

6. The method of claim 1 wherein:

the current sequence is accessed as an array of columns and rows, with bits in the array being received from the communication network one column after another column; and

the bits of the first set are comprised in a single row of the array.

7. The method of claim 6 wherein:

the array comprises a left group of columns and a right group of columns; and

during said receiving, receipt of columns in the current sequence alternates between a column in the left group and a column in the right group.

8. The method of claim 7 wherein:

a right-most column in the left group and a left-most column in the right group are received after receipt of a left-most column in the left group and a right-most column in the right group.

9. The method of claim 1 further comprising:

using locations of said errors in a currently decoded codeword to determine a plurality of remainders of additional codewords that intersect with said currently decoded codeword at said locations;

counting a number of said remainders that are equal to zero, for said additional codewords;

checking if said number satisfies a predetermined condition; and

when the predetermined condition is satisfied correcting said errors and when the predetermined condition is not satisfied skipping said correcting.

10. The method of claim 1 further comprising:

using locations of said errors in a currently decoded codeword to determine a plurality of remainders of additional codewords that intersect with said currently decoded codeword at said locations;

checking if a first remainder in said plurality of remainders is not present in any of a plurality of constituent decoders;

wherein said plurality of constituent decoders perform said checking of the plurality of codewords; and

when a first result of said checking is false, disabling use of said first remainder by one of said constituent decoders.

11. The method of claim 10 further comprising:

when said first result is true, further checking whether a first index of said first remainder is greater than a largest index of any codeword currently being decoded; and

when a second result of said further checking is true and said first remainder after update is non-zero, adding said first remainder after update to a pool of remainders for decoding.

12. The method of claim 11 further comprising:

when said second result is false and said first remainder after update is non-zero, marking said first remainder after update as being available for decoding in the next iteration of decoding.

13. A non-transitory computer-readable storage medium comprising:

instructions to one or more processors to receive a current sequence of bits from a communication network;

instructions to the one or more processors to check for errors in a plurality of codewords that are grouped into multiple groups;

wherein each codeword has a first set of said bits comprised within the current sequence and a second set of said bits comprised in a plurality of past sequences that are received by execution of said instructions prior to receipt of the current sequence;

wherein each codeword in a group has no bit in common with another codeword in said group; and

wherein each codeword in said group has a bit in common with another codeword in another group;

wherein the first set and the second set together comprise message bits and parity bits of said each codeword; and

instructions to the one or more processors to store in memory coupled thereto, a result obtained at least partially based on execution of said instructions to check.

14. A circuit comprising:

means for receiving a current sequence of bits from a communication network;

means for checking for errors in a plurality of codewords that are grouped into multiple groups;

wherein each codeword has a first set of said bits comprised within the current sequence and a second set of said bits comprised in a plurality of past sequences that are received by execution of said instructions prior to receipt of the current sequence;

wherein each codeword in a group has no bit in common with another codeword in said group; and

wherein each codeword in said group has a bit in common with another codeword in another group;

wherein the first set and the second set together comprise message bits and parity bits of said each codeword; and

means for storing in memory, a result obtained at least partially by operation of said means for checking.

15. A method of encoding comprising:

in a processor,

using a current word of bits in a sequence to update, based on a concurrent code, at least one of several storage elements in an initial set;

wherein the initial set is one of several sets included in one group of storage elements;

shifting all bits in the current word cyclically to obtain a cyclically-shifted current word;

using the cyclically-shifted current word to update one of several storage elements in another set;

wherein said another set is another one of several sets included in another group of storage elements; and

repeating said usings and said shiftings with additional words occurring in said sequence subsequent to said current word.

16. The method of claim 15 further comprising:

forming a first new word using a number of bits of each of the storage elements in the initial set; and

transmitting to a communication network, at least the first new word as parity.

17. The method of claim 16 further comprising:

shifting all bits in the first new word cyclically to obtain a cyclically-shifted first new word; and

using the cyclically-shifted first new word to update at least one of several storage elements in said another set.

Assignments (3)
SECURITY INTEREST Recorded May 11, 2017
From: MACOM CONNECTIVITY SOLUTIONS, LLC (SUCCESSOR TO APPLIED MICRO CIRCUITS CORPORATION)
To: GOLDMAN SACHS BANK USA, AS COLLATERAL AGENT
Reel/Frame 042444/0891 →
MERGER AND CHANGE OF NAME Recorded Apr 6, 2017
From: APPLIED MICRO CIRCUITS CORPORATION; MACOM CONNECTIVITY SOLUTIONS, LLC; MACOM CONNECTIVITY SOLUTIONS, LLC
To: MACOM CONNECTIVITY SOLUTIONS, LLC
Reel/Frame 042176/0185 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2011
From: TONG, PO; DJURDJEVIC, IVANA; LATREMOUILLE, DAMIEN; CAGGIONI, FRANCESCO; DABIRI, DARIUSH
To: APPLIED MICRO CIRCUITS CORPORATION
Reel/Frame 026854/0091 →