Prefetch tag for eviction promotion
View Patent ↗Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.
1. A cache prefetch system, comprising:
an interconnect configured for communicably coupling a processor, a shared cache, and a main memory;
a processor cache prefetcher configured for prefetching a set of data from the main memory via the interconnect for storage in a processor cache, wherein the processor cache is associated with the processor, and wherein the processor cache prefetcher tags a first portion of data of the set of data as unused data to indicate that the first portion of data has not been used by the processor, has a first probability of a first future use by the processor, and is to be sent from the processor cache to the shared cache, and tags a second portion of data associated with the set of data as used data to indicate that the second portion of data has been used by the processor and is to be sent from the processor cache to the main memory, wherein the first probability of the first future use is based on a probability that the processor will use the first portion of data within a defined period of time; and
a processor cache evictor configured for evicting the first portion of data from the processor cache to the shared cache via the interconnect, based on the first portion of data being tagged as the unused data, and evicting the second portion of data from the processor cache to the main memory via the interconnect based on the second portion of data being tagged as the used data.
2. The cache prefetch system of claim 1 , wherein the interconnect comprises a ring interconnect.
3. The cache prefetch system of claim 1 , wherein the processor cache comprises a level 2 cache, and the shared cache comprises a level 3 cache.
4. The cache prefetch system of claim 1 , wherein the set of data comprises first data that is executed by the processor, and second data that is associated with the first data.
5. The cache prefetch system of claim 4 , wherein the second data is determined to be related to the first data based on a determination that a first address space associated with the first data is within a defined proximity to a second address space associated with the second data in the main memory.
6. The cache prefetch system of claim 1 , wherein the processor cache prefetcher is further configured for tagging the first portion of data with a first tag that indicates the first probability of the first future use of the first portion of data by the processor and the second portion of data with a second tag that indicates a second probability of a second future use of the second portion of data by the processor.
7. The cache prefetch system of claim 1 , wherein the processor cache prefetcher is further configured for prefetching the set of data from the main memory via the interconnect for storage in the processor cache, in response to not identifying, in the processor cache, a memory location associated with at least a portion of the set of data.
8. The cache prefetch system of claim 1 , wherein the processor cache prefetcher is further configured for prefetching the first portion of data from the shared cache in response to the processor requesting the first portion of data.
9. The cache prefetch system of claim 1 , wherein the shared cache is shared by a plurality of processors comprising the processor.
10. A cache prefetch system comprising:
a processor; and
a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising:
prefetching a set of data from a system memory for storage in a processor cache, associated with the processor;
tagging a first portion of data associated with the set of data with a first indication that the first portion of data is executed data that was executed by the processor and is to be sent from the processor cache to the system memory;
tagging a second portion of data of the set of data with a second indication based on determining that the second portion of data has been unused by the processor and is predicted to be executed by the processor within a defined period of time, wherein the second portion of data is determined to have a defined probability of being executed by the processor within the defined period of time; and
evicting the second portion of data from the processor cache to a shared cache based on the tagging of the second portion of data.
11. The cache prefetch system of claim 10 , wherein the operations further comprise:
evicting the first portion of data from the processor cache to the system memory based on the first indication.
12. The cache prefetch system of claim 10 , wherein the operations further comprise:
prefetching the evicted second portion of data from the shared cache to the processor cache in response to receiving, from the processor, a request to execute the second portion of data.
13. The cache prefetch system of claim 10 , wherein the processor, the system memory, and the shared cache are communicably coupled via a ring interconnect.
14. The cache prefetch system of claim 10 , wherein a first latency to retrieve data from the shared cache is less than a second latency to retrieve data from the system memory.
15. The cache prefetch system of claim 10 , wherein the first portion of data is requested in a data request and the second portion of data is not requested in the data request, wherein the first portion of data and the second portion of data are determined to be related to each other based on a logical proximity and a physical proximity of the first portion of data and the second portion of data to each other in the system memory, and wherein the first portion of data and the second portion of data are prefetched from the system memory for storage in the processor cache in response to the data request based on the first portion of data and the second portion of data being determined to be related to each other.
16. A caching method, comprising:
prefetching a set of data from a system memory for storage in a processor cache, the processor cache associated with the processor;
tagging a first portion of data associated with the set of data with a first indicator that indicates the first portion of data is used data that was used by the processor and is to be communicated from the processor cache to the system memory;
tagging a second portion of data of the set of data with a second indicator that indicates the second portion of data is unused data and is to be communicated from the processor cache to a shared cache based on determining that the second portion of data has been unused by the processor and is predicted to be used by the processor within a defined period of time, wherein the second portion of data is determined to have a defined probability of being used by the processor within a predetermined period of time; and
evicting the second portion of data from the processor cache to the shared cache based on the tagging of the second portion of data with the second indicator.
17. The caching method of claim 16 , further comprising:
evicting the first portion of data from the processor cache to the system memory based on the tagging of the first portion of data with the first indicator.
18. The caching method of claim 16 , further comprising:
prefetching the evicted second portion of data from the shared cache to the processor cache in response to receiving a request to execute the second portion of data from the processor.
19. The caching method of claim 16 , wherein the prefetching and the evicting are via a ring interconnect coupling the processor, the system memory, and the shared cache.
20. The caching method of claim 16 , further comprising:
setting a first indicator bit to a first value to facilitate the tagging of the first portion of data with the first indicator; and
setting a second indicator bit to a second value to facilitate the tagging of the second portion of data with the second indicator.