Digital CMOS circuit with noise cancellation
View Patent ↗A system is provided with a digital complementary-metal-oxide-semiconductor (CMOS) device and a noise cancellation circuit. The CMOS device has a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply a binary logic output signal, and a fourth interface connected to a first dc voltage (e.g., ground) to sink current. A first resistor is interposed between a second dc voltage (e.g., Vdd), with a potential higher than the first dc voltage, and the second interface of the CMOS device. The noise cancellation circuit has a first interface connected to the second dc voltage. The noise cancellation circuit high pass filters ac noise on the second dc voltage, amplifies the filtered noise, and supplies the amplified noise at a second interface connected to the second interface of the CMOS device.
1. A system with a digital complementary-metal-oxide-semiconductor (CMOS) device and a noise cancellation circuit, the system comprising:
a CMOS device having a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply a binary logic output signal, and a fourth interface connected to a first dc voltage to sink current;
a first resistor interposed between a second dc voltage, with a potential higher than the first dc voltage, and the second interface of the CMOS device; and,
a noise cancellation circuit having a first interface connected to the second dc voltage, the noise cancellation circuit high pass filtering ac noise on the second dc voltage, amplifying the filtered noise, and supplying the amplified noise at a second interface connected to the second interface of the CMOS device.
2. The system of claim 1 wherein the noise cancellation circuit includes:
a first field effect transistor (FET) having a source connected to the first dc voltage, a drain connected to the second interface of the CMOS device, and a gate;
a first capacitor having a first terminal connected to the second dc voltage and a second terminal connected to the first FET gate;
a second resistor having a first terminal connected to the second dc voltage and a second terminal connected to the first FET gate; and,
a third resistor having a first terminal connected the first FET gate and a second terminal connected to the first dc voltage.
3. The system of claim 2 further comprising:
a first plurality of CMOS devices, each having a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply the binary logic output signal, and a fourth interface connected to a first dc voltage to sink current;
a first plurality of resistors interposed between the second dc voltage and the second interface of each CMOS device; and,
wherein the noise cancellation circuit includes a first plurality of FETs, each having a source connected to the first dc voltage, a drain connected to the second interface of a corresponding CMOS device, and a gate connected to second terminal of the first capacitor.
4. The system of claim 1 wherein the noise cancellation circuit includes:
a first FET having a source connected to the first dc voltage, a drain connected to the second interface of the CMOS device, and a gate;
a second VET having a drain connected to the second dc voltage, a source connected to the gate of the first VET, and a gate;
a second capacitor having a first terminal connected to the first dc voltage and a second terminal connected to the second FET gate;
a second resistor having a first terminal connected to the second dc voltage and a second terminal connected to the second FET gate;
a third resistor having a first terminal connected the second FET gate and a second terminal connected to the first dc voltage; and,
a load interposed between the source of the second FET and the first dc voltage.
5. The system of claim 4 wherein the load is selected from a group consisting of a passive and active load.
6. The system of claim 5 wherein the active load includes:
a third FET having a drain connected to the source of the second VET, a gate, and a source connected to the first dc voltage; and,
a fourth resistor having a first terminal connected to the gate of the third FET and a second terminal connected to the source of the second FET.
7. The system of claim 6 wherein the active load further includes a third capacitor having a first terminal connected to the gate of the third FET and a second terminal connected to the first dc voltage.
8. The system of claim 4 further comprising:
a first plurality of CMOS devices, each having a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply the binary logic output signal, and a fourth interface connected to a first dc voltage to sink current;
a first plurality of resistors interposed between the second dc voltage and the second interface of each CMOS device; and,
wherein the noise cancellation circuit includes a first plurality of first FETs, each first FET having a source connected to the first dc voltage, a drain connected to the second interface of a corresponding CMOS device, and a gate connected to the source of the second FET.
9. The system of claim 1 wherein the CMOS device is selected from a group consisting of an inverter and a buffer.
10. The system of claim 1 wherein the first resistor supplies the source current with the ac noise; and,
wherein the noise cancellation circuit supplies the amplified noise opposite in phase to the ac noise.
11. The system of claim 1 wherein the noise cancellation circuit second interface supplies the amplified noise as an amplified noise current.
12. The system of claim 1 further comprising:
a first plurality of CMOS devices, each having a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply the binary logic output signal, and a fourth interface connected to a first dc voltage to sink current;
a first plurality of resistors interposed between the second dc voltage and the second interface of each CMOS device;
wherein the noise cancellation circuit includes a first plurality of first FETs, each first FET having a source connected to the first dc voltage, a drain connected to the second interface of a corresponding CMOS device, and a gate;
a second FET having a drain connected to the second dc voltage, a source connected to the gate of each first FET, and a gate;
a second capacitor having a first terminal connected to the first dc voltage and a second terminal connected to the second FET gate;
a second resistor having a first terminal and a second terminal connected to the second VET gate;
a third resistor having a first terminal connected the first terminal of the second resistor and a second terminal connected to the first dc voltage;
a load interposed between the source of the second FET and the first dc voltage; and,
a third FET having a drain connected to the second dc voltage, a gate connected to the first terminal of the second resistor, and a source connected to the first terminal of the second resistor.
13. A method for canceling power supply noise in a complementary-metal-oxide-semiconductor (CMOS) device, the method comprising:
providing a CMOS device having a power interface connected to receive a supply voltage with an ac noise component;
accepting a binary logic input signal to the CMOS device;
high pass filtering noise on the supply voltage to create a filtered noise current;
amplifying the filtered noise current to create an amplified noise current;
supplying the amplified noise voltage to the CMOS device power interface; and,
canceling the ac noise component supplied to the CMOS device power interface with the amplified noise current.
14. The method of claim 13 further comprising:
supplying a binary logic output signal from the CMOS device, without the ac noise component.
15. A method for canceling power supply noise in a complementary-metal-oxide-semiconductor (CMOS) device, the method comprising:
providing a CMOS device having a power interface connected to receive a supply voltage with an ac noise component;
accepting a binary logic input signal to the CMOS device;
a means for high pass filtering noise on the supply voltage to create a filtered noise current;
a means for amplifying the filtered noise current to create an amplified noise current;
a means for supplying the amplified noise voltage to the CMOS device power interface; and,
a means for canceling the ac noise component supplied to the CMOS device power interface with the amplified noise current.