Method for manufacturing a photodetector having a bandwidth tuned honeycomb cell photodiode structure
View Patent ↗A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.
1. A method for fabricating a photodetector with a bandwidth-tuned cell structure, the method comprising:
providing a semiconductor substrate heavily doped with a first dopant;
forming a plurality of adjoining cavities in the semiconductor substrate having shared cell walls;
forming a semiconductor well in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant;
growing a layer of oxide overlying the semiconductor wells;
annealing the semiconductor wells;
forming a metal pillar extending into each semiconductor well having a central axis aligned with an optical path;
forming a first electrode connected to the metal pillar of each cell; and,
forming a second electrode connected to the semiconductor substrate.
2. The method of claim 1 further comprising:
decreasing a capacitance between the first and second electrodes in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.
3. The method of claim 1 further comprising:
providing a bias voltage to the first and second electrodes;
accepting an optical signal;
measuring a higher bandwidth response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter.
4. The method of claim 1 further comprising:
providing a bias voltage to the first and second electrodes;
accepting an optical signal;
measuring a higher quantum efficiency (QE) in response to forming a decreased number of semiconductor wells with an increased diameter, and forming metal pillars with an increased diameter.
5. The method of claim 1 further comprising:
providing a bias voltage to the first and second electrodes;
accepting an optical signal at a wavelength in a range of about 815 to 875 nanometers (nm);
wherein forming the semiconductor well in each cavity includes forming silicon wells;
wherein forming the metal pillars includes:
forming an opening in each semiconductor well having an aspect ratio (L/d) of at least 7:1, where L is defined as a depth of the opening and d is defined as the opening diameter at a top surface of the cell well; and,
depositing metal in the opening.
6. The method of claim 5 wherein forming the opening in each semiconductor well includes each opening having a ratio d/d0 of less than 10:1, where d0 is defined as the opening diameter at a bottom surface of the cell well.
7. The method of claim 1 wherein forming the plurality of adjoining cavities includes forming cavities with a number of cell walls selected from a group consisting of 1 through 6, where a 1-sided wall is defined by a shape selected from a group consisting of oval and circular.