Frequency synthesis with gapper
View Patent ↗Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.
1. An integrated circuit for frequency synthesis, said integrated circuit comprising:
a gapper configured to generate a first gapped signal based on an input signal;
a first frequency divider coupled with said gapper and configured to receive said first gapped signal and generate a second gapped signal; and
a phase locked loop (PLL) configured to receive said second gapped signal and generate an output signal, wherein, if a frequency ratio of said input signal to said output signal is less than 1, said gapper is configured to incorporate an factor that is greater than 1 from said first frequency divider.
2. The integrated circuit of claim 1 , wherein said first frequency divider comprises a first integer divider, and wherein said PLL comprises:
a second integer divider having a second integer divide ratio and operable to generate said output signal; and
a third integer divider disposed in a feedback loop of said PLL and configured to generate a feedback signal by dividing said output signal with a third integer divide ratio.
3. The integrated circuit of claim 2 , wherein said gapper comprises:
a gapping unit configured to generate said first gapped signal that comprises an equivalent of Q pulses responsive to P pulses of said input signal in accordance with a plurality of gapping control signals, wherein P is greater than or equal to Q; and
a control unit comprising a Delta Sigma Modulator (DSM) that is configured to generate said plurality of gapping control signals,
wherein, if said frequency ratio is greater than or equal to 1, P/Q is approximately equal to said frequency ratio, and
wherein, if said frequency ratio is less than 1, P/Q is approximately equal to said frequency ratio multiplied by said factor, wherein said factor is an integer.
4. The integrated circuit of claim 3 ,
wherein, if said frequency ratio is greater than or equal to 1, said first, said second and said third integer divide ratio are all equal, and
wherein, if said frequency ratio is less than 1, said second and said third integer divide ratios are equal, and said first integer divide ratio is equal to said second integer divide ratio divided by said factor.
5. The integrated circuit of claim 3 , wherein said gapping unit is operable to remove a half pulse during a clock cycle in accordance with a respective gapping control signal.
6. The integrated circuit of claim 3 , wherein said DSM comprises:
a clock input to receive a clock signal;
a first register configured to store a first number;
a second register configured to store a stored value;
an adder coupled with said first and said second register, wherein said adder is configured to add said first number with said stored value to generate a sum; and
a modulo component coupled with said adder and configured to generate a remainder of said sum modulo a second number to update said stored value, and to output an overflow,
wherein said control unit is operable to generate said plurality of gapping control signals based on comparison between overflows and a predetermined value.
7. The integrated circuit of claim 6 , wherein said gapping unit is configured to remove a 1/K portion of a pulse from said input signal during a clock cycle in accordance with a gapping control signal, wherein K is a positive integer.
8. The integrated circuit of claim 7 , wherein said first number is equal to K(P−Q), and said second number is equal to P, and wherein a respective gapping control signal is generated upon determination that a corresponding overflow is greater than or equal to P.
9. The integrated circuit of claim 6 , wherein said gapping unit comprises a multi-modulus divider configured to divide said input signal with a sequence of divide ratios, wherein an average of said divide ratios is approximately equal to P/Q, and wherein said sequence of divide ratio are converted from said plurality of gapping control signals.
10. The integrated circuit of claim 9 , wherein said first number is equal to 2(P−Q), wherein said second number is equal to Q, wherein said sequence of divide ratios comprises a first divide ratio equal to 1 and a second divide ratio equal to 1.5, and wherein a respective gapping control signal is generated in response to a determination that a corresponding overflow is equal to or greater than Q.
11. A method of frequency synthesis, said method comprising:
generating a first gapped signal based on an input signal;
dividing said first gapped signal with a first divide ratio in a first frequency divider to generate a second gapped signal;
generating an output signal based on said second gapped signal; and
if a frequency ratio of said input signal to said output signal is less than 1, incorporating a factor that is greater than 1 from said first frequency divider while generating said first gapped signal.
12. The method of claim 11 ,
wherein said first gapped signal comprises an equivalent of Q pulses corresponding to P pulses in said input signal, wherein P and Q are integers and P is greater than Q;
wherein said first divide ratio and said factor are integers;
wherein, if said frequency ratio is less than 1 P/Q is approximately equal to said frequency ratio multiplied by said factor; and
wherein further, if said first frequency ratio is greater than or equal to 1, P/Q is approximately equal to said frequency ratio.
13. The method of claim 12 further comprising:
providing said second gapped signal to a PLL;
attenuating jitter from said second gapped signal;
multiplying said second gapped signal with a second integer divide ratio; and
outputting said output signal.
14. The method of claim 12 , wherein generating said first gapped signal comprises:
receiving a clock signal;
deriving a first number and a second number from P and Q; and
generating a plurality of gapping control signals by, during a clock cycle of said clock signal,
deriving a remainder of a stored value modulo said second number;
adding said remainder with said first number to update said stored value;
detecting an overflow resulted from said adding said remainder with said first number; and
generating a gapping control signal based on a difference between a value of said overflow and a predetermined value.
15. The method of claim 14 ,
wherein said clock signal is coupled with said input signal,
wherein said first number is equal to K(P−Q) and said second number is equal to P, wherein K is a positive integer,
wherein said predetermined value is equal to P, and
wherein generating said first gapped signal further comprises removing 1/K portion of a pulse from said input signal during a respective clock cycle in response to a corresponding gapping control signal, where K is a positive integer.
16. The method of claim 14 , wherein generating said first gapped signal further comprising dividing said input signal by a sequence of divide ratios in response to said plurality of gapping control signals, wherein an average of said sequence of divide ratios is approximately equal to P/Q, and wherein said clock signal is coupled with said first gapped signal.
17. An integrated system comprising:
a gapper configured to generate a first gapped signal that comprises an equivalent of Q pulses based on P pulses in an input signal, wherein P and Q are integers and P is greater than Q;
a first integer divider configured to divide said first gapped signal to generate a second gapped signal;
a Phase Locked Loop (PLL) comprising one or more integer dividers and configured to attenuate jitter from said second gapped signal and generate an output signal;
wherein, if a frequency ratio of said input signal to said output signal is less than 1, said gapper is operable to borrow a factor that is greater than 1 from said first integer divider such that P/Q is approximately equal to said frequency ratio multiplied by said factor.
18. The integrated system of claim 17 ,
wherein further, if said frequency ratio is equal to or greater than 1, P/Q is approximately equal to said frequency ratio; and
wherein said PLL comprises:
a phase frequency detector configured to detect a phase difference between said second gapped signal and a feedback signal of said PLL, and generate an error signal based on said phase difference;
a Digital-Controlled Oscillator (DCO) coupled with said phase detector and configured to generate an oscillated signal in response to said error signal;
a second integer divider coupled with said DCO and configured to generate said output signal by dividing said oscillated signal with a second integer divide ratio; and
a third integer divider coupled with said second integer divider and configured to generate said feedback signal by dividing said output signal with a third integer divide ratio, wherein said second integer divide ratio is equal to said third integer divide ratio.
19. The system of claim 17 , wherein said gapper is further configured to remove a fraction of a pulse from said input signal during a clock cycle of a clock signal.
20. The system of claim 17 , wherein said gapper comprises a Delta Sigma Modulator (DSM) comprising a clock input, a first register, a second register, an adder, and a modulo component.