IP Library Granted Patent US 9,483,977
Granted Patent B2
US 9,483,977 · App. 11/723,210 · Granted Nov 1, 2016

Light emitting display device and driving method thereof

Inventor: Chang Ho Hyeon (Yongin-si, KR)
Assignee: LG Display Co., Ltd.
G09G3/3233G09G3/2022G09G3/2074G09G3/3225G09G5/393G09G5/399G09G3/2044G09G2300/0842G09G2320/0247G09G2320/0261G09G2320/0266G09G2320/103
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,483,977
App. No.
11/723,210
Granted
Nov 1, 2016
Kind
B2
Abstract

A method of driving an organic light emitting display device includes: receiving an image signal by sub-field with respect to a single frame comprising the N number of sub-fields (N is a natural number greater than 2) from the exterior; dividing a single sub-field into an address period and a display period and selectively calling a data signal of a single sub-field from the M number of sub-field memories (M is a natural number greater than 2); and applying the called data signal of the single sub-field to a sub-pixel.

Claims (50)

1. A method of driving an organic light emitting display device having a plurality of sub-pixels, the method comprising:

receiving image signals by sub-fields with respect to a single frame comprising the N number of sub-fields per sub-pixel (N is a natural number greater than 2) from the exterior;

selecting fewer than all of real gray levels represented by the N sub-fields;

half-toning the selected real gray levels to generate a plurality of in-between gray levels, different from the real gray levels;

storing, in a first sub-field memory among an M number of sub-field memories, the selected real gray levels and the in-between gray levels;

dividing a single sub-field into an address period and a display period and selectively calling a data signal of the single sub-field from the M number of sub-field memories (M is a natural number greater than 1), a data signal being stored in a capacitor of a sub-pixel during the address period, an organic light emitting diode of the sub-pixel being illuminated during the address period and the display period; and

applying the called data signal of the single sub-field to the sub-pixel,

wherein the sub-field memories include the first sub-field memory and a second sub-field memory,

wherein the first sub-field memory creates a first sub-field mapping code table of the sub-fields to express real gray levels of a still image by a combination of the N number of sub-fields, and

wherein the second sub-field memory creates a second sub-field mapping code table in which all the remaining sub-fields except for a maximum sub-field of the first sub-field memory to express gray levels lower than the gray levels expressed by the first sub-field memory, a display period of the maximum sub-field having a maximum binary weight.

2. The method of claim 1 , further comprising gamma-correcting the image signals.

3. The method of claim 1 , wherein:

N is 6 or 16; and

M is 2.

4. The method of claim 1 , wherein some of the sub-fields are divided into multiple groups and data signals with respect to the sub-fields are called from the sub-field memories.

5. The method of claim 4 , wherein the same M number of sub-field memories that call one or more data signals of the N number of sub-fields are changeable.

6. The method of claim 1 , further comprising creating a third sub-field mapping code table having buffering sub-fields larger than buffering sub-fields of the first and second sub-field mapping code tables.

7. An organic light emitting display device, comprising:

a main memory that receives image signals by sub-fields with respect to a single frame comprising the N number of sub-fields per sub-pixel from the exterior;

a half-tone circuit configured to select fewer than all of real gray levels represented by the N sub-fields and to half-tone the selected real gray levels to generate a plurality of in-between gray levels, different from the real gray levels; and

a sub-field memory unit that comprises an M number of sub-field memories that divide a single sub-field into an address period and a display period and selectively call a data signal of the single sub-field, a data signal being stored in a capacitor of a sub-pixel during the address period, an organic light emitting diode of the sub-pixel being illuminated during the address period and the display period;

wherein the sub-field memories include a first sub-field memory configured to store the selected real gray levels and the in-between gray levels and a second sub-field memory,

wherein the first sub-field memory creates a first sub-field mapping code table of the sub-fields to express real gray levels of a still image by a combination of the N number of sub-fields,

wherein the second sub-field memory creates a second sub-field mapping code table in which all the remaining sub-fields except for a maximum sub-field of the first sub-field memory to express gray levels lower than the gray levels expressed by the first sub-field memory, a display period of the maximum sub-field has a maximum binary weight.

8. The device of claim 7 , further comprising a gamma correction circuit that gamma-corrects the image signals.

9. The device of claim 7 , wherein:

N is 6 or 16; and

M is 2.

10. The device of claim 7 , wherein some of the sub-fields are divided into multiple groups and a data signal with respect to the sub-fields is called from the sub-field memories.

11. The device of claim 10 , wherein the same M number of sub-field memories that call one or more data signals of the N number of sub-fields are changeable.

12. The device of claim 7 , wherein the sub-field memory unit creates a third sub-field mapping code table having buffering sub-fields larger than buffering sub-fields of the first and second sub-field mapping code tables.

13. An organic light emitting display device, comprising:

a display unit comprising a plurality of sub-pixels;

a host memory comprising an N number of bits representing an N number of sub-fields for each sub-pixel, the host memory being configured to receive an image data from an external source, where N is a natural number greater than 2;

a half-tone circuit configured to:

select fewer than a 2 N number of real gray levels represented by the N sub-fields; and

half-tone the selected real gray levels to generate a plurality of in-between gray levels different from the real gray levels;

a sub-field memory unit including a first sub-field memory and a second sub-field memory, the sub-field memory unit being configured to store the selected real gray levels and the in-between gray levels in a P number of sub-fields for each sub-pixel, where P is a natural number greater than N; and

a digital-to-analog converter configured to convert data from the sub-field memory unit into an analog signal supplied to the display unit.

14. The device of claim 13 , wherein the first sub-field memory is configured to create a first sub-field mapping table using the selected real gray levels and the in-between gray levels to express a still image.

15. The device of claim 14 , wherein the second sub-field memory is configured to:

create a second sub-field mapping table with all of the sub-fields except for a maximum sub-field of the first mapping table; and

use the second sub-field mapping table as a false contour buffering mapping table.

16. The device of claim 15 , wherein the sub-field memory unit is further configured to create a third sub-field mapping code table having buffering sub-fields larger than buffering sub-fields of the second sub-field mapping code table.

17. The device of claim 13 , wherein the first sub-field memory and the second sub-field memory each have a P number of bits to represent the P number of sub-fields for each sub-pixel.

18. The device of claim 13 , wherein:

the first sub-field memory and the second sub-field memory each have an N number of bits for each sub-pixel; and

the first sub-field memory and the second sub-field memory are configured to divide the N bits into the P number of sub-fields.

19. The device of claim 18 , wherein, when one of the sub-fields is called, bit data is called from each of the first sub-field memory and the second sub-field memory.

20. The device of claim 13 , further comprising a gamma correction circuit configured to gamma-correct the image data.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2008
From: LG ELECTRONICS INC.
To: LG DISPLAY CO., LTD.
Reel/Frame 020845/0783 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2007
From: HYEON, CHANG HO
To: LG ELECTRONICS INC.
Reel/Frame 019083/0557 →
Continuity (1)
Related Publication 20080231565A1 · Sep 25, 2008