Nonvolatile semiconductor memory device
View Patent ↗A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property are improved.
1. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,
wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,
wherein the first layer is in contact with the first insulating layer and includes a semiconductor material,
wherein a band gap of the first layer is smaller than a band gap of the channel formation region in the semiconductor substrate, and
wherein the first layer comprises an n-type impurity.
2. The nonvolatile semiconductor memory device according to claim 1 ,
wherein the first insulating layer comprises a stacked layer of a silicon oxide layer and a silicon nitride layer.
3. The nonvolatile semiconductor memory device according to claim 2 , wherein the floating gate is in contact with the silicon nitride layer.
4. The nonvolatile semiconductor memory device according to claim 2 ,
wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and
wherein the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.
5. The nonvolatile semiconductor memory device according to claim 1 , wherein a difference between the band gap of the channel formation region in the semiconductor substrate and the band gap of the first layer is 0.1 eV or greater.
6. An electronic device having the nonvolatile semiconductor memory device according to claim 1 , wherein the electronic device is one selected from the group consisting of a camera, sound reproducing device, a computer, game machine, a mobile information terminal, and an image reproducing device.
7. The nonvolatile semiconductor memory device according to claim 1 , wherein the first layer comprises germanium.
8. The nonvolatile semiconductor memory device according to claim 1 , wherein the second layer comprises a silicon compound.
9. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,
wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,
wherein the first layer is in contact with the first insulating layer,
wherein the first layer has an electron affinity which is larger than an electron affinity of the channel formation region in the semiconductor substrate, and
wherein the first layer comprises an n-type impurity.
10. The nonvolatile semiconductor memory device according to claim 9 ,
wherein the first insulating layer comprises a stacked layer of a silicon oxide layer and a silicon nitride layer.
11. The nonvolatile semiconductor memory device according to claim 10 , wherein the floating gate is in contact with the silicon nitride layer.
12. The nonvolatile semiconductor memory device according to claim 10 ,
wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and
wherein the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.
13. An electronic device having the nonvolatile semiconductor memory device according to claim 9 , wherein the electronic device is one selected from the group consisting of a camera, sound reproducing device, a computer, game machine, a mobile information terminal, and an image reproducing device.
14. The nonvolatile semiconductor memory device according to claim 9 , wherein the first layer comprises germanium.
15. The nonvolatile semiconductor memory device according to claim 9 , wherein the second layer comprises a silicon compound.
16. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,
wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,
wherein barrier energy with respect to electrons in the first layer of the floating gate, formed by the first insulating layer, is higher than barrier energy with respect to electrons in the channel formation region in the semiconductor substrate, formed by the first insulating layer, and
wherein the first layer comprises an n-type impurity.
17. The nonvolatile semiconductor memory device according to claim 16 ,
wherein the first insulating layer comprises a stacked layer of a silicon oxide layer and a silicon nitride layer.
18. The nonvolatile semiconductor memory device according to claim 17 , wherein the floating gate is in contact with the silicon nitride layer.
19. The nonvolatile semiconductor memory device according to claim 17 ,
wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and
wherein the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.
20. An electronic device having the nonvolatile semiconductor memory device according to claim 16 , wherein the electronic device is one selected from the group consisting of a camera, sound reproducing device, a computer, game machine, a mobile information terminal, and an image reproducing device.
21. The nonvolatile semiconductor memory device according to claim 16 , wherein the first layer comprises germanium.
22. The nonvolatile semiconductor memory device according to claim 16 , wherein the second layer comprises a silicon compound.
23. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,
wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,
wherein the first layer is in contact with the first insulating layer,
wherein the first layer comprises germanium and an n-type impurity.
24. The nonvolatile semiconductor memory device according to claim 23 ,
wherein the first insulating layer comprises a stacked layer of a silicon oxide layer and a silicon nitride layer.
25. The nonvolatile semiconductor memory device according to claim 24 , wherein the floating gate is in contact with the silicon nitride layer.
26. The nonvolatile semiconductor memory device according to claim 24 ,
wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and
wherein the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.
27. The nonvolatile semiconductor memory device according to claim 23 , wherein the first layer is formed of germanium added with the n-type impurity.
28. The nonvolatile semiconductor memory device according to claim 23 , wherein the first layer is formed of a germanium compound added with the n-type impurity.
29. The nonvolatile semiconductor memory device according to claim 23 , wherein the first layer is formed of a germanium oxide added with the n-type impurity or germanium nitride added with the n-type impurity.
30. An electronic device having the nonvolatile semiconductor memory device according to claim 23 , wherein the electronic device is one selected from the group consisting of a camera, sound reproducing device, a computer, game machine, a mobile information terminal, and an image reproducing device.
31. The nonvolatile semiconductor memory device according to claim 23 , wherein a thickness of the first insulating layer is 1 nm or more and 20 nm or less.
32. The nonvolatile semiconductor memory device according to claim 23 , wherein the second layer comprises a silicon compound.
33. A semiconductor device comprising:
an antenna;
a memory circuit comprising:
a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,
wherein the antenna is operationally connected to the memory circuit,
wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,
wherein the first layer is in contact with the first insulating layer and includes a semiconductor material,
wherein a band gap of the first layer is smaller than a band gap of the channel formation region in the semiconductor substrate, and
wherein the first layer comprises an n-type impurity.
34. The semiconductor device according to claim 33 , wherein the antenna is operationally connected to the memory circuit through a high frequency circuit, a reset circuit and a control circuit.
35. A semiconductor device comprising:
an antenna;
a memory circuit comprising:
a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,
wherein the antenna is operationally connected to the memory circuit,
wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,
wherein the first layer is in contact with the first insulating layer,
wherein the first layer has an electron affinity which is larger than an electron affinity of the channel formation region in the semiconductor substrate, and
wherein the first layer comprises an n-type impurity.
36. The semiconductor device according to claim 35 , wherein the antenna is operationally connected to the memory circuit through a high frequency circuit, a reset circuit and a control circuit.
37. A semiconductor device comprising:
an antenna;
a memory circuit comprising:
a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,
wherein the antenna is operationally connected to the memory circuit,
wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,
wherein barrier energy with respect to electrons in the first layer of the floating gate, formed by the first insulating layer, is higher than barrier energy with respect to electrons in the channel formation region in the semiconductor substrate, formed by the first insulating layer, and
wherein the first layer comprises an n-type impurity.
38. The semiconductor device according to claim 37 , wherein the antenna is operationally connected to the memory circuit through a high frequency circuit, a reset circuit and a control circuit.
39. A semiconductor device comprising:
an antenna;
a memory circuit comprising:
a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,
wherein the antenna is operationally connected to the memory circuit,
wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,
wherein the first layer is in contact with the first insulating layer,
wherein the first layer comprises germanium, and
wherein the first layer comprises an n-type impurity.
40. The semiconductor device according to claim 39 , wherein the antenna is operationally connected to the memory circuit through a high frequency circuit, a reset circuit and a control circuit.
41. The semiconductor device according to claim 39 , wherein the first insulating layer comprises a stacked layer of a silicon oxide layer and a silicon nitride layer.
42. The semiconductor device according to claim 41 , wherein the floating gate is in contact with the silicon nitride layer.
43. The semiconductor device according to claim 41 , wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and
wherein the silicon nitride layer is formed by nitriding the silicon oxide layer by plasma treatment.
44. The nonvolatile semiconductor memory device according to claim 1 ,
wherein one of the pair of impurity regions is located between the channel formation region and one of the pair of field oxide films.
45. The nonvolatile semiconductor memory device according to claim 9 ,
wherein one of the pair of impurity regions is located between the channel formation region and one of the pair of field oxide films.
46. The nonvolatile semiconductor memory device according to claim 16 ,
wherein one of the pair of impurity regions is located between the channel formation region and one of the pair of field oxide films.
47. The nonvolatile semiconductor memory device according to claim 23 ,
wherein one of the pair of impurity regions is located between the channel formation region and one of the pair of field oxide films.
48. The semiconductor device according to claim 33 ,
wherein one of the pair of impurity regions is located between the channel formation region and one of the pair of field oxide films.
49. The semiconductor device according to claim 35 ,
wherein one of the pair of impurity regions is located between the channel formation region and one of the pair of field oxide films.
50. The semiconductor device according to claim 37 ,
wherein one of the pair of impurity regions is located between the channel formation region and one of the pair of field oxide films.
51. The semiconductor device according to claim 39 ,
wherein one of the pair of impurity regions is located between the channel formation region and one of the pair of field oxide films.
52. The nonvolatile semiconductor memory device according to claim 1 , wherein a concentration of the n-type impurity is 1×10 18 cm −3 to 2×10 20 cm −3 .
53. The nonvolatile semiconductor memory device according to claim 9 , wherein a concentration of the n-type impurity is 1×10 18 cm −3 to 2×10 20 cm −3 .
54. The nonvolatile semiconductor memory device according to claim 16 , wherein a concentration of the n-type impurity is 1×10 18 cm −3 to 2×10 20 cm −3 .
55. The nonvolatile semiconductor memory device according to claim 23 , wherein a concentration of the n-type impurity is 1×10 18 cm −3 to 2×10 20 cm −3 .
56. The semiconductor device according to claim 33 , wherein a concentration of the n-type impurity is 1×10 18 cm −3 to 2×10 20 cm −3 .
57. The semiconductor device according to claim 35 , wherein a concentration of the n-type impurity is 1×10 18 cm −3 to 2×10 20 cm −3 .
58. The semiconductor device according to claim 37 , wherein a concentration of the n-type impurity is 1×10 18 cm −3 to 2×10 20 cm −3 .
59. The semiconductor device according to claim 39 , wherein a concentration of the n-type impurity is 1×10 18 cm −3 to 2×10 20 cm −3 .
60. The nonvolatile semiconductor memory device according to claim 1 , wherein a band gap of the second layer is larger than the band gap of the first layer.
61. The nonvolatile semiconductor memory device according to claim 9 , wherein a band gap of the second layer is larger than a band gap of the first layer.
62. The nonvolatile semiconductor memory device according to claim 16 , wherein a band gap of the second layer is larger than a band gap of the first layer.
63. The nonvolatile semiconductor memory device according to claim 23 , wherein a band gap of the second layer is larger than a band gap of the first layer.
64. The semiconductor device according to claim 33 , wherein a band gap of the second layer is larger than the band gap of the first layer.
65. The semiconductor device according to claim 35 , wherein a band gap of the second layer is larger than a band gap of the first layer.
66. The semiconductor device according to claim 37 , wherein a band gap of the second layer is larger than a band gap of the first layer.
67. The semiconductor device according to claim 39 , wherein a band gap of the second layer is larger than a band gap of the first layer.