Optimizing a circuit design
View Patent ↗Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.
1. A method for optimizing a circuit design including a plurality of nets, comprising:
reconfiguring a circuit design using a processor to incrementally improve timing by increasing spacing between wires, wherein timing improvements reduce capacitances of one or more nets;
reconfiguring the circuit design to incrementally improve expected manufacturing yield by converting one or more single-cut vias into double-cut vias, wherein yield improvements increase capacitances of one or more nets; and
evaluating the effects of one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield to determine whether one or more of the timing and yield have improved.
2. A method as recited in claim 1 , wherein timing improvements are achieved by spreading wires.
3. A method as recited in claim 1 , wherein yield improvements are achieved by converting one or more single-cut vias into double-cut vias.
4. A method as recited in claim 1 , wherein a grid-less or shape-based routing technology is employed for one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield.
5. A method as recited in claim 1 , wherein increasing spacing between wires comprises pushing away one or more neighboring wires from one or more nets.
6. A method as recited in claim 1 , wherein evaluating comprises analyzing a timing of the circuit design.
7. A method as recited in claim 1 , further comprising determining a target timing delay for the circuit design.
8. A method as recited in claim 7 , wherein the target timing delay is based at least in part on one or more of a potential for spreading wires and a desired yield for the circuit design.
9. A method as recited in claim 7 , further comprising updating the target timing delay based at least in part on one or more of an ability to reconfigure the circuit design to improve timing, an ability to reconfigure the circuit design to improve yield, and the effects of one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield.
10. A method as recited in claim 1 , further comprising reverting to a previous configuration of the circuit design if one or more of the timing and yield have not improved.
11. A method as recited in claim 1 , wherein improvements in timing are used to reduce a timing delay of the circuit.
12. A method as recited in claim 1 , wherein improvements in timing are used to improve yield.
13. A method as recited in claim 1 , further comprising determining a capacitance budget for each of one or more nets and wherein one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield are based at least in part on one or more capacitance budgets.
14. A method as recited in claim 13 , wherein the capacitance budget of each net is based on one or more of a potential to push neighboring wires away from the net and a potential to convert one or more single-cut vias associated with the net into double-cut vias.
15. A method as recited in claim 1 , wherein one or more of reconfiguring the circuit design to improve timing, reconfiguring the circuit design to improve yield, and evaluating the effects of one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield are iteratively performed to optimize the circuit design.
16. A method as recited in claim 1 , wherein reconfiguring the circuit design to improve timing includes evaluating the effects of reconfiguring the circuit design to improve timing to determine whether timing has improved.
17. A system for optimizing a circuit design including a plurality of nets, comprising:
a processor configured to:
reconfigure a circuit design to incrementally improve timing by increasing spacing between wires, wherein timing improvements reduce capacitances of one or more nets;
reconfigure the circuit design to incrementally improve expected manufacturing yield by converting one or more single-cut vias into double-cut vias, wherein yield improvements increase capacitances of one or more nets; and
evaluate the effects of one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield to determine whether one or more of the timing and yield have improved; and
a memory coupled to the processor and configured to provide instructions to the processor.
18. A system as recited in claim 17 , wherein a grid-less or shape-based routing technology is employed for one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield.
19. A system as recited in claim 17 , wherein increasing spacing between wires comprises pushing away one or more neighboring wires from one or more nets.
20. A system as recited in claim 17 , wherein to evaluate comprises analyzing a timing of the circuit design.
21. A system as recited in claim 17 , wherein one or more of reconfiguring the circuit design to improve timing, reconfiguring the circuit design to improve yield, and evaluating the effects of one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield are iteratively performed to optimize the circuit design.
22. A computer program product for optimizing a circuit design including a plurality of nets, the computer program product being embodied in a computer readable storage medium and comprising computer instructions configured to cause a computer to:
reconfigure the circuit design to incrementally improve timing by increasing spacing between wires, wherein timing improvements reduce capacitances of one or more nets;
reconfigure the circuit design to incrementally improve expected manufacturing yield by converting one or more single-cut vias into double-cut vias, wherein yield improvements increase capacitances of one or more nets; and
evaluate the effects of one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield to determine whether one or more of the timing and yield have improved.
23. A computer program product as recited in claim 22 , wherein a grid-less or shape-based routing technology is employed for one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield.
24. A computer program product as recited in claim 22 , wherein one or more of reconfiguring the circuit design to improve timing, reconfiguring the circuit design to improve yield, and evaluating the effects of one or more of reconfiguring the circuit design to improve timing and reconfiguring the circuit design to improve yield are iteratively performed to optimize the circuit design.