Patent Assignment
Reel/Frame 030820/0490
Assignment of Assignor's Interest
Recorded: 2013-07-17
Pages: 7
Assignor
SPRINGSOFT USA, INC.
Executed: 2013-07-12
Assignee
SYNOPSYS, INC.
700 E. MIDDLEFIELD RD., MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(55)
Incremental Simulation Using Previous Simulation Results and Knowledge of Changes to Simulation Model to Achieve Fast Simulation Time
Patent:
6,321,363 →
Application:
09/228,905 →
Rule-Driven Method and System for Editing Physical Integrated Circuit Layouts
Patent:
6,341,366 →
Application:
09/232,467 →
System and Method for Browsing Graphically an Electronic Design Based on a Hardware Description Language Specification
Patent:
6,366,874 →
Application:
09/317,691 →
Method and System for Analyzing Test Coverage
Patent:
6,691,079 →
Application:
09/322,185 →
Method and System for Constructing and Manipulating a Physical Integrated Circuit Layout of a Multiple-Gate Semiconductor Device
Patent:
6,457,163 →
Application:
09/480,063 →
Circuit Property Verification System
Patent:
6,985,840 →
Application:
09/630,348 →
Prioritized Debugging of an Error Space in Program Code
System for Characterizing Simulated Circuit Logic and Behavior
Automatic Schematic Diagram Generation Using Topology Information
Ic Behavior Analysis System
Patent:
7,079,997 →
Application:
10/143,347 →
Method and System for Creating Test Component Layouts
Circuit Simulation Bus Transaction Analysis
Scripted, Hierarchical Template-Based Ic Physical Layout System
Schematic Diagram Generation and Display System
Unit-Based Layout System for Passive Ic Devices
Ic Compaction System
Rule-Based Schematic Diagram Generator
Incremental Circuit Re-Simulation System
Debugging System for Gate Level Ic Designs
Ic Functional and Delay Fault Testing
Method of Testing High-Speed Ic with Low-Speed Ic Tester
Application:
11/470,312 →
Publication:
US 2008/0082880
Multilevel Ic Floorplanner
Method and System for Evaluating Computer Program Tests by Means of Mutation Analysis
Method for Evaluating a Test Program Quality
Method for Evaluating the Quality of a Computer Program
V-Shaped Multilevel Full-Chip Gridless Routing
Timing of a Circuit Design
Patent:
7,917,881 →
Application:
11/725,188 →
Optimizing a Circuit Design
Patent:
7,739,630 →
Application:
11/725,191 →
Template-Based Gateway Model Routing System
Analog and Mixed Signal Ic Layout System
Analog Ic Placement Using Symmetry-Islands
A Hierarchy-Based Analytical Placement Method for an Integrated Circuit
System for Implementing Post-Silicon Ic Design Changes
Methods and Systems for Reducing Clock Skew in a Gated Clock Tree
Hierarchical Analog Ic Placement Subject to Symmetry, Matching and Proximity Constraints
Power-Aware Debugging
Circuit Emulation Systems and Methods
Method for Improving Yield Rate Using Redundant Wire Insertion
Systems and Methods for Designing and Making Integrated Circuits with Consideration of Wiring Demand Ratio
Method and Apparatus for Versatile Controllability and Observability in Prototype System
Method and Apparatus for Transaction Recording and Visualization
Method of Recording and Replaying Call Frames for the Testbench
Hierarchial Power Map for Low Power Design
Methods for Generating Device Layouts by Combining an Automated Device Layout Generator with a Script
What-If Simulation Methods and Systems
Multiple Level Spine Routing
Multiple Level Spine Routing
Viewing and Debugging Hdl Designs Having Systemverilog Interface Constructs
Method of Speeding Up Access to Design Databases Having Large Numbers of Design Units
Method and Apparatus for Versatile Controllability and Observability in Prototype System
Compact Routing
Patent:
8,832,632 →
Application:
13/660,887 →
Systems and Methods for Designing and Making Integrated Circuits with Consideration of Wiring Demand Ratio
Design automation
Application:
60/831,257 →
Two-Level Spine Routing
Application:
61/417,839 →
Compact Net Routing
Application:
61/552,409 →
Related Assignments
(14)
Other recorded transfers of the patents in this record — the chain of ownership.
Re-Record to Correct the Receiving Party's Name, Previously Recorded at Reel 9710, Frame 0094.
Dec 8, 2003
From: WANG, JUI-CHIEN; LI, YIH-LANG
To: SPRINGSOFT INC.
Reel/Frame 014759/0986 →
Re-Record to Correct the Name of the Assignee, Previously Recorded on Reel 010524 Frame 0155, Assignor Confirms the Assignment of the Entire Interest.
Dec 22, 2003
From: YANG, LU-TSANN
To: SPRINGSOFT INC.
Reel/Frame 014805/0729 →
Assignment of Assignor's Interest
Mar 15, 2004
From: TSAI, JIEN-SHEN; YEH, NAN-TING; LU, MOU-TIEN; CHEN, CHUNG-CHIA
To: SPRINGSOFT, INC.
Reel/Frame 014426/0762 →
Assignment of Assignor's Interest
Jun 24, 2004
From: LIN, CHIA-CHI; WANG, JUI-CHIAN; CHANG, MIN-WEN
To: SPRINGSOFT, INC.
Reel/Frame 014771/0744 →
Assignment of Assignor's Interest
Nov 16, 2004
From: LIN, PO-HUNG; LIN, SHYH-CHANG
To: SPRINGSOFT, INC.
Reel/Frame 015368/0614 →
Assignment of Assignor's Interest
Feb 17, 2005
From: TANG, SHYH-AN; HSU, YA-CHIN
To: SPRINGSOFT, INC.
Reel/Frame 015696/0131 →
Assignment of Assignor's Interest
Mar 8, 2005
From: YANG, LU-TSANN; TSAI, CHUN-CHI
To: SPRINGSOFT, INC.
Reel/Frame 015742/0588 →
Assignment of Assignor's Interest
Aug 3, 2005
From: TSAI, TIAN-HAU; LIN, PO-HUNG; LIN, SHYH-CHANG; YU, HO-CHE
To: SPRINGSOFT, INC.
Reel/Frame 016365/0247 →
Assignment of Assignor's Interest
Dec 14, 2005
From: CHANG, YING-TSAI; LIU, TAYUNG; HSU, YU-CHIN
To: NOVAS SOFTWARE, INC.
Reel/Frame 016893/0616 →
Assignment of Assignor's Interest
Mar 7, 2006
From: HSU, YU-CHIN; TSAI, FURSHING; JONG, WORI-TZY
To: NOVAS SOFTWARE, INC.
Reel/Frame 017266/0717 →
Assignment of Assignor's Interest
Dec 2, 2008
From: SPRINGSOFT, INC.
To: SPRINGSOFT USA, INC.
Reel/Frame 021901/0906 →
Assignment of Assignor's Interest
Dec 5, 2008
From: NOVAS SOFTWARE, INC.
To: SPRINGSOFT USA, INC.
Reel/Frame 021924/0497 →
Assignment of Assignor's Interest
May 11, 2016
From: SPRINGSOFT USA, INC.
To: SYNOPSYS, INC.
Reel/Frame 038552/0440 →
Merger
May 11, 2016
From: FORTELINK INC.; NOVAS SOFTWARE, INC.
To: SPRINGSOFT USA, INC.
Reel/Frame 038552/0322 →