Methods and systems for reducing clock skew in a gated clock tree
View Patent ↗Systems and methods for synthesizing a gated clock tree with reduced clock skew are provided. A gated clock tree circuit with reduced clock skew may include a clock source and edge-triggered state elements. A gated clock tree disposed between the clock source and state elements may include a level in which each logic gate has a common logic type. Logic gates in the gated clock tree may also be configured as logic-gate buffers. The logic gates may also be configured as NAND-gated equivalents. The clock signal distributed through the gated clock tree may drive both positive-edge-triggered and negative-edge-triggered state elements.
1. A computer-implemented method for synthesizing a gated clock tree with reduced clock skew comprising the following computer-implemented stages:
providing a clock source operable to generate a clock signal;
providing a plurality of edge-triggered state elements;
providing a gated clock tree between the clock source and the plurality of edge-triggered state elements, wherein the gated clock tree comprises a level, wherein the level includes a plurality of logic gates; and
matching, using a processor, the plurality of logic gates in the level such that each logic gate in the level has a common logic type.
2. The method of claim 1 , wherein the matching further comprises configuring at least one of the plurality of logic gates as one of a logic-gate buffer and a NAND-gate equivalent.
3. The method of claim 2 , wherein configuring the plurality of logic gates further comprises:
determining whether/the plurality of logic gates in the level have more than one type of non-buffer logic types; and
transforming each of the plurality of logic gates into a NAND-gate equivalent if the plurality of logic gates in the level include more than one type of non-buffer logic types.
4. The method of claim 2 , wherein configuring the plurality of logic gates further comprises:
determining whether the plurality of logic gates in the level have more than one type of non-buffer logic types; and
transforming each of the plurality of logic gates that are buffer-type into logic-gate buffers if the plurality of logic gates includes only one type of non-buffer logic types.
5. The method of claim 1 , wherein providing a gated clock tree further comprises converting a pre-existing gated clock tree into the gated clock tree.
6. The method of claim 1 , further comprising configuring the gated clock tree such that each of the plurality of logic gates in the level has a matching load.
7. The method of claim 6 , wherein configuring the gated clock tree further comprises:
performing a clustering process; and
providing at least one additional logic gate to the level based on the clustering process.
8. The method of claim 7 , wherein the method further comprises determining, by the clustering process, a sum of clusters and adding to the level a number of additional logic gates that equals the sum of clusters.
9. The method of claim 1 , wherein providing a plurality of edge-triggered state elements further comprises providing at least one positive-edge-triggered state element and one negative-edge-triggered state element.
10. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, performs a method comprising:
providing a clock source operable to generate a clock signal;
providing a plurality of edge-triggered state elements;
providing a gated clock tree between the clock source and the plurality of edge-triggered state elements, wherein the gated clock tree comprises a level, wherein the level includes a plurality of logic gates; and
matching the plurality of logic gates in the level such that each logic gate in the level has a common logic type.
11. The computer-readable storage medium of claim 10 , wherein the matching further comprises configuring at least one of the plurality of logic gates as one of a logic-gate buffer and a NAND-gate equivalent.
12. The computer-readable storage medium of claim 11 , wherein matching the plurality of logic gates further comprises:
determining whether the plurality of logic gates in the level have more than one type of non-buffer logic types; and
transforming each of the plurality of logic gates into a NAND-gate equivalent if the plurality of logic gates in the level include more than one type of non-buffer logic types.
13. The computer-readable storage medium of claim 11 , wherein matching the plurality of logic gates further comprises:
determining whether the plurality of logic gates in the level have more than one type of non-buffer logic types; and
transforming each of the plurality of logic gates that are buffer-type into logic-gate buffers if the plurality of logic gates in the level do not include more than one type of non-buffer logic types.
14. The computer-readable storage medium of claim 10 , further comprising configuring the gated clock tree such that each of the plurality of logic gates in the level has a matching load.
15. The computer-readable storage medium of claim 14 , wherein configuring the gated clock tree further comprises:
performing a clustering process; and
providing at least one additional logic gate to the level based on the clustering process.
16. The computer-readable storage medium of 15 , further comprising determining, by the clustering process, a sum of clusters and adding to the level a number of additional gates that equals the sum of clusters.
17. The computer-readable storage medium of claim 10 , wherein providing a plurality of edge-triggered state elements further comprises providing at least one positive-edge-triggered state element and one negative-edge-triggered state element.
18. A computer-implemented method for synthesizing a gated clock tree with reduced clock skew comprising the following computer-implemented stages:
providing a clock source operable to generate a clock signal;
providing a plurality of edge-triggered state elements;
providing a gated clock tree between the clock source and the plurality of edge-triggered state elements, wherein the gated clock tree comprises a level, wherein the level includes a plurality of logic gates;
matching, by a computer, the plurality of logic gates in the level such that each logic gate in the level has a common logic type, wherein matching the plurality of logic gates comprises:
determining whether the plurality of logic gates in the level have more than one type of non-buffer logic types; and
transforming each of the plurality of logic gates into a NAND-gate equivalent if the plurality of logic gates in the level include more than one type of non-buffer logic types.