Compact routing
View Patent ↗Techniques for compacting routing in lower level blocks to free routing resources for upper level blocks are disclosed. In some embodiments, a specification of a hierarchical integrated circuit design comprising a lower level block and an upper level block is obtained. The specification includes an initial routing plan for the lower level block. Subsequently, a compacted routing plan for the lower level block using constrained routing resources comprising fewer routing tracks than the initial routing plan and resulting in at least one unused track as well as a routing plan for the upper level block using the at least one unused track are generated.
1. A system configured to:
obtain a specification of a hierarchical integrated circuit design comprising a lower level block and an upper level block when the system is invoked to route the hierarchical integrated circuit design, wherein the specification comprises a first routing plan associated with the lower level block;
modify the first routing plan using constrained routing resources so as to generate a second routing plan associated with the lower level block, the second routing plan comprising fewer routing tracks than the first routing plan and resulting in at least one unused track; and
generate a third routing plan associated with the upper level block using the at least one unused track.
2. The system of claim 1 , wherein the specification includes a specification of available routing resources.
3. The system of claim 1 , wherein the first routing plan is generated without imposing constraints on available routing resources.
4. The system of claim 1 , wherein using the at least one unused track facilitates a straight routing in the upper level block.
5. The system of claim 1 , wherein the constrained routing resources comprise a set of allowed routing tracks that is a subset of a set of all available routing tracks.
6. The system of claim 5 , wherein the set of allowed routing tracks comprises a minimum number of routing tracks associated with routing the lower level block.
7. The system of claim 5 , wherein a number of tracks in the set of allowed routing tracks is equal to a maximal number of parallel wires in the set of all available routing tracks that intersects a line perpendicular to the set of all available routing tracks.
8. The system of claim 5 , wherein the set of allowed routing tracks includes tracks comprising a maximal number of parallel wires in the set of all available routing tracks that intersects a line perpendicular to the set of all available routing tracks.
9. The system of claim 5 , wherein blockage constraints are inserted with respect to tracks not included in the set of allowed routing tracks but included in the set of available routing tracks so that the blocked tracks are not used in association with routing the lower level block.
10. The system of claim 5 , wherein the set of allowed routing tracks is selected using a modified k-means clustering algorithm.
11. The system of claim 10 , wherein the modified k-means clustering algorithm is based on a cost function.
12. The system of claim 11 , wherein the cost function is based at least in part on displacements of moving wires.
13. The system of claim 11 , wherein the cost function is based at least in part on preferred routing tracks or areas.
14. The system of claim 1 , wherein the system is further configured to iteratively re-route the second routing plan after relaxing or removing one or more routing resource constraints when the second routing plan includes an error until a fourth routing plan is achieved that does not include the error.
15. The system of claim 14 , wherein DRC (Design Rule Checking) violations are permitted in association with intermediate routing plans generated during re-routing iterations but not in association with the fourth routing plan.
16. The system of claim 14 , wherein wire overlapping is permitted in association with intermediate routing plans generated during re-routing iterations but not in association with the fourth routing plan.
17. The system of claim 1 , wherein the first routing plan comprises a partial routing plan.
18. A computer-implemented method, comprising:
obtaining, using the computer, a specification of a hierarchical integrated circuit design comprising a lower level block and an upper level block when the computer is invoked to route the hierarchical integrated circuit design, wherein the specification comprises a first routing plan associated with the lower level block;
modifying, using the computer, the first routing plan using constrained routing resources so as to generate a second routing plan associated with the lower level block, the second routing plan comprising fewer routing tracks than the first routing plan and resulting in at least one unused track; and
generating, using the computer, a third routing plan associated with the upper level block using the at least one unused track.
19. The computer-implemented method of claim 18 further comprising iteratively re-routing the second routing plan after relaxing or removing one or more routing resource constraints when the second routing plan includes an error until a fourth routing plan is achieved that does not include the error.
20. A non-transitory computer readable storage medium comprising instructions which when executed by a computer cause the computer to:
obtain a specification of a hierarchical integrated circuit design comprising a lower level block and an upper level block when the computer is invoked to route the hierarchical integrated circuit design, wherein the specification comprises a first routing plan associated with the lower level block;
modify the first routing plan using constrained routing resources so as to generate a second routing plan associated with the lower level block, the second routing plan comprising fewer routing tracks than the first routing plan and resulting in at least one unused track; and
generate a third routing plan associated with the upper level block using the at least one unused track.