Viewing and debugging HDL designs having SystemVerilog interface constructs

1. A computer implemented method for viewing and debugging an HDL design having SystemVerilog interface constructs, comprising:

receiving, with one or more processors associated with a computer, an HDL design code, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct; and

displaying, with the one or more processors, a first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the SystemVerilog interface construct in a schematic view,

wherein the interface object is disposed between the first and second objects,

wherein interface signals from the first object to the second object and interface signals from the second object to the first object pass through the interface object.

2. The computer implemented method as claimed in claim 1 , wherein a shape of the interface object is a double arrow, and each shape of the first and second objects is a rectangle.

3. The computer implemented method as claimed in claim 1 , wherein the first object has a first module port coupled to a second module port of the interface object for transferring of the interface signals between the first and second objects, and the second object has a third module port coupled to a fourth module port of the interface object for transferring of the interface signals between the first and second objects, wherein the first and third module ports have the same shape, which is different from other ports of the first and second object.

4. The computer implemented method as claimed in claim 3 , wherein the shapes of the first, second, third and fourth module ports are identical.

5. The computer implemented method as claimed in claim 3 , wherein the second and fourth module ports are disposed on the first and second sides of the interface object, and the first object is disposed on the outside of the second module port of the interface object and the second object is disposed on the outside of the fourth module port of the interface object, wherein the second side is opposite to the first side on the interface object.

6. The computer implemented method as claimed in claim 5 , wherein the first module is a master or driver module and the second module is a slave or load module when a quantity of the interface signals from the first object to the second object is larger than that of the interface signals from the second object to the first object, and the second and fourth module ports are disposed on the left hand side and the right hand side of the interface object, respectively.

7. The computer implemented method as claimed in claim 1 , further comprising:

selecting, with the one or more processors, the interface object to display connectivity information of all of the interface signals and module ports inside the interface object.

8. The computer implemented method as claimed in claim 7 , wherein the step of selecting the interface object to display connectivity information of all the interface signals and module ports inside the interface object further comprises:

annotating, with the one or more processors, simulation values on the interface signals.

9. The computer implemented method as claimed in claim 7 , further comprising:

selecting, with the one or more processors, one connection line or one module port to trace connectivity thereof; and

displaying, with the one or more processors, the traced result.

10. The computer implemented method as claimed in claim 9 , wherein the traced result comprises the objects inside the module objects that are connected to the selected connection line or the selected module port.

11. The computer implemented method as claimed in claim 1 , further comprising:

selecting, with the one or more processors, the interface object to display waveform information of the interface signals in a waveform view.

12. The computer implemented method as claimed in claim 11 , further comprising:

selecting, with the one or more processors, one waveform that represents an unknown value in the waveform view to trace the interface signal that causes the unknown value; and

displaying, with the one or more processors, a driver object of the traced interface signal in the schematic view.

13. The computer implemented method as claimed in claim 1 , further comprising:

selecting, with the one or more processors, the interface object to display the code of the SystemVerilog interface construct in a code view.

14. A system for viewing and debugging an HDL design having SystemVerilog interface constructs, comprising:

a processing unit, receiving an HDL design code, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct; and

a display unit coupled to the processing unit,

wherein the processing unit controls the display unit to open a schematic view, and displays a first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct in the schematic view,

wherein the interface object is disposed between the first and second objects,

wherein the interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.

15. The system as claimed in claim 14 , wherein a shape of the interface object is a double arrow, and each shape of the first and second objects is a rectangle.

16. The system as claimed in claim 14 , wherein the first object has a first module port coupled to a second module port of the interface object for transferring of the interface signals between the first and second objects, and the second object has a third module port coupled to a fourth module port of the interface object for transferring of the interface signals between the first and second objects, wherein the first and third module ports have the same shape, which is different from other ports of the first and second object.

17. The system as claimed in claim 16 , wherein the shapes of the first, second, third and fourth module ports are identical.

18. The system as claimed in claim 16 , wherein the second and fourth module ports are disposed on the first and second sides of the interface object, and the first object is disposed on the outside of the second module port of the interface object and the second object is disposed on the outside of the fourth module port of the interface object, wherein the second side is opposite to the first side on the interface object.

19. The system as claimed in claim 18 , wherein the first module is a master or driver module and the second module is a slave or load module when a quantity of the interface signals from the first object to the second object is larger than that of the interface signals from the second object to the first object, and the second and fourth module ports are disposed on the left hand side and the right hand side of the interface object, respectively.

20. The computer implemented method as claimed in claim 1 , wherein a shape of the interface object is different from that of the first and second objects.

21. The system as claimed in claim 14 , wherein a shape of the interface object is different from that of the first and second objects.