Semiconductor device with improved power supply arrangement
View Patent ↗A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
1. A semiconductor device comprising:
first and second memory banks including a plurality of sense amplifiers and adapted to be activated by first and second commands, respectively;
a power supply line adapted to supply a predetermined voltage to the plurality of sense amplifiers of said first and second memory banks and arranged in a mesh manner above the first and second memory banks; and
first and second power supply circuits having respective output nodes connected to said power supply line, said first and said second power supply circuits being adapted to generate said predetermined voltage;
wherein said first power supply circuit are adapted to start generating said predetermined voltage in response to said first command; and
wherein, when said second command is inputted while said first memory bank is active, said first power supply circuit is adapted to stop generating said predetermined voltage in response to said second command and said second power supply circuit is adapted to start generating said predetermined voltage in response to said second command.
2. The semiconductor device according to claim 1 ,
wherein, when said second command is inputted while said first memory bank is active, said first power supply circuit is adapted to stop generating said predetermined voltage upon elapse of a predetermined period of time after said second power supply circuit has started generating said predetermined voltage.
3. The semiconductor device according to claim 1 ,
wherein, when a third command which designates to deactivate said first and said second memory banks is inputted simultaneously, one of said first and said second power supply circuits currently generating said predetermined voltage is adapted to stop generating said predetermined voltage in response to said third command.
4. The semiconductor device according to claim 1 ,
wherein, when a fourth command which designates to refresh a plurality of memory cells included in said first and said second memory banks is inputted, said first and said second power supply circuits are adapted to start generating a first voltage in response to said fourth command, and wherein said first and said second power supply circuits are adapted to stop generating said first voltage upon elapse of a predetermined period of time.