IP Library Granted Patent US 7,695,766
Granted Patent B2
US 7,695,766 · App. 11/732,087 · Granted Apr 13, 2010

Method of identifying specific holes in an interface guiding plate

Assignee: Circuit Check
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Quick Facts
Patent No.
US 7,695,766
App. No.
11/732,087
Granted
Apr 13, 2010
Kind
B2
Abstract

A circuit board tester that uses a dual-stage translation to bring a unit under test (UUT) into physical and electric contact first with a series of tall probes, then with a series of short probes. Initially, the UUT is mounted on a support plate, and spaced apart from both the tall and short probes. First, in order to perform a functional test on the UUT, a first vacuum stage is engaged, and atmospheric pressure translates the UUT longitudinally until contact is made with a first hard stop, defining a first position. At this first position, the UUT is in contact with a series of tall probes, and is spaced apart from a series of short probes. After a function test is performed, a second vacuum stage is engaged in addition to, and independent of, the first vacuum stage. Atmospheric pressure translates the UUT longitudinally until contact is made with a second hard stop, defining a second position.

Claims (26)

1. A method of identifying specific holes in a board interface guiding plate having a surface of first predetermined surface color, said plate intended to receive contact pins to pass through said specific holes, the method comprising:

a) firmly adhering an indicator colorant of a second predetermined color to said surface at least surrounding each of said holes;

b) removing the indicator colorant generally circumferentially around selected holes which are to be left populated or conversely unpopulated with pins, so that holes can be distinguished from each other;

c) populating as a group either the selected or unselected holes with pins; and

d) visually verifying that holes which are to be populated with pins are present in the appropriate holes and absent in all others as determined by the presence or absence of colorant.

2. The method of claim 1 wherein the indicator is a colorant and wherein the colorant is visually distinguishable by contrast from the predetermined surface color and wherein the step of removing said colorant is ablation.

3. The method of claim 1 wherein the indicator is a colorant and wherein the colorant is visually distinguishable by contrast from the predetermined surface color and wherein the step of removing said colorant is countersinking by drilling.

4. The method of claim 1 wherein the indicator is a colorant and wherein the colorant is visually distinguishable by contrast from the predetermined surface color and wherein the step of removing said colorant is lasering.

5. The method of claim 1 wherein the holes which have the colorant removed are populated with pins.

6. The method of claim 1 wherein the holes which do not have the colorant removed are populated with pins.

7. The method of claim 1 wherein the holes are drilled into the plate in a regular matrix of rows and columns.

8. A method of identifying specific holes in a non circuit board interface guiding plate having a surface of first predetermined surface color, said plate intended to receive contact pins to pass through specific holes, the method comprising:

a) forming a plurality of holes in the interface plate to form a matrix of columns and rows of holes;

b) overcoating said surface with a coating having a second predetermined surface color, said overcoating second color being different from said plate surface color;

c) determining which of the holes in the matrix are to be identified for populating with said contact pins; and

d) removing said overcoating around such holes as are determined to be populated; so that visual inspection of the plate will easily identify holes intended to be populated by the lack of overcoating adjacent said holes.

9. The method of claim 8 further including populating on the holes where the overcoating is removed.

10. The method of claim 8 further including populating on the holes where the overcoating is not removed.

11. The method of claim 8 wherein the overcoating is removed by countersink drilling of selected holes.

12. The method of claim 8 wherein the overcoating is removed by abating.

13. The method of claim 8 wherein the overcoating is removed by lasering.

14. A method of preparing a board interface guiding plate for using in a circuit testing device, said plate having a matrix of holes in rows and columns to be located in a circuit board testing device, some of the holes to be populated by probes which will extend through the holes and engage an electronic circuit board when the board and probes are brought together by the testing device, said plate having a surface of first predetermined surface color, said plate intended to receive contact pins in specific holes, the method comprising:

a) forming a plurality of holes in the interface plate to form a matrix of columns and rows of holes;

b) overcoating said surface with a coating having a second predetermined surface color, said overcoating second color being different from said plate surface color;

c) determining which of the holes in the matrix are to be identified for populating with said contact pins; and

d) removing said overcoating around such holes as are determined to be populated; so that visual inspection of the plate will easily identify holes intended to be populated by the lack of overcoating adjacent said holes.

Assignments (3)
SECURITY INTEREST Recorded Feb 9, 2024
From: CIRCUIT CHECK, INC.
To: CIBC BANK USA
Reel/Frame 066430/0721 →
SECURITY INTEREST Recorded Dec 28, 2015
From: CIRCUIT CHECK, INC.
To: THE PRIVATEBANK AND TRUST COMPANY
Reel/Frame 037363/0104 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2014
From: STAGGERT, SCOTT
To: CIRCUIT CHECK
Reel/Frame 031976/0580 →
Continuity (4)
Division 1086716400 · Jun 14, 2004
Provisional Application 6057226300 · May 18, 2004
Provisional Application 6057231500 · May 18, 2004
Related Publication 20080231299A1 · Sep 25, 2008