Switched-capacitor reset architecture for opamp

1. A pipelined analog to digital converter (ADC) comprising a plurality of pipelined stages, each stage comprising an analog to digital converter comprising a pair of comparators outputting signals to a multiplying digital to analog converter (MDAC), and the MDAC comprising an opamp and a reset circuit for the opamp, wherein the reset circuit including first and second capacitor elements and switching circuitry for precharging each of the first and second capacitor elements to the difference between input and output common-mode voltages of the opamp, and wherein during a reset phase of the MDAC, connecting the first capacitor between a positive input and a negative output of the opamp and connecting the second capacitor between a negative input and a positive output of the opamp to reset the opamp.

2. The ADC of claim 1 wherein the switching circuitry precharges the first and second capacitor elements during an operational phase of the MDAC.

3. The ADC of claim 2 wherein the opamp operates in a closed loop configuration in both the reset phase and the operational phase.

4. The ADC of claim 3 wherein the opamp is a multi-stage opamp having a folded cascode architecture.

5. The ADC of claim 1 wherein the plurality of pipelined stages includes a first pipelined state whose MDAC includes the largest opamp of all the pipelined stages.

6. The ADC of claim 1 wherein the pipelined stages are each 1.5 bit stages abd the ADC comprises a 2-bit flash analog to digital converter connected to a final 1.5 bit stage of the plurality of 1.5 bit stages; and

an error correct and summing circuit connected to receive output from each of the 1.5 bit stages and the 2-bit flash analog to digital converter.

7. The ADC of claim 6 wherein the ADC is a 10-bit pipelined ADC and the number of pipelined 1.5 bit stages is eight.

8. The ADC of claim 7 wherein the ADC is fabricated in a 0.18 □m logic CMOS technology.

9. The ADC of claim 1 wherein each capacitor element consists of a single capacitor.

10. A reset circuit in combination with an opamp, the reset circuit including:

first and second capacitor elements; and

switching circuitry for: (i) during an operational phase of the opamp, connecting the first and second capacitor elements to voltage sources to charge the first and second capacitor elements; and (ii) during a reset phase of the opamp, connecting the first capacitor element between a positive input and a negative output of the opamp and connecting the second capacitor element between a negative input and a positive output of the opamp to reset the opamp.

11. The reset circuit of claim 10 wherein the opamp operates in a closed loop configuration in both the reset phase and the operational phase.

12. The reset circuit of claim 11 wherein during the operational phase, the switching circuitry connects each of the first and second capacitor elements between voltages that are equal the opamp input and output common mode voltages.

13. The reset circuit of claim 10 wherein the opamp and switching circuitry are part of a multiplying digital to analog converter (MDAC).

14. The reset circuit of claim 13 wherein the MDAC is part of a pipelined stage for a pipelined analog to digital converter.

15. The reset circuit of claim 10 wherein the opamp is a multi-stage opamp having a folded cascode architecture.

16. A method of resetting an opamp in a multiplying digital to analog converter (MDAC) of a pipelined stage of a multi-stage pipelined analog to digital converter, comprising:

pre-charging first and second capacitor elements during an operational phase of the opamp; and

during a reset phase of the MDAC, connecting the first capacitor element between an input and an output of the opamp and connecting the second capacitor between a further input and a further output of the opamp to reset the opamp.

17. The method of claim 16 wherein the opamp operates in a closed loop configuration in both the reset phase and the operational phase.

18. The method of claim 17 wherein precharging the first and second capacitor elements includes connecting each of the capacitor elements between voltages that are equal to the opamp input and opamp output common mode voltages.

19. The method of claim 18 wherein during the reset phase, the first capacitor element is connected between a positive input and a negative output of the opamp and the second capacitor element is connected between a negative input and a positive output of the opamp.

20. The method of claim 16 wherein the opamp is a multi-stage opamp having a folded cascode architecture, the pipelined stage is a 1.5 bit stage, and the capacitor elements each consist of a single capacitor.