Patent Assignment
Reel/Frame 065017/0449
Assignment of Assignor's Interest
Recorded: 2023-09-22
Pages: 18
Assignor
RAMBUS INC.
Executed: 2023-09-06
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(140)
Duty-Cycle Correction Circuit
System and Method for Jitter Control
Method and Apparatus for Generating Unique Identification Numbers for Pci Express Transactions with Substantially Increased Performance
Switched-Capacitor Reset Architecture for Opamp
Serializer Deserializer Circuits
Decision Feedback Equalizer and Transceiver
High-Speed Sst Transmit Driver
Application:
13/611,421 →
High-Speed Sst Transmit Driver
Patent:
8,878,568 →
Application:
13/658,980 →
Deserialized Dual-Loop Clock Radio and Data Recovery Circuit
Deserialized Dual-Loop Clock Radio and Data Recovery Circuit
Signal Receiver with Skew-Tolerant Strobe Gating
Patent:
10,325,636 →
Application:
15/945,235 →
High-Resolution Digitally Controlled Delay Line
Patent:
11,183,995 →
Application:
15/945,523 →
Skew-Tolerant Timing Signal Gating
Patent:
10,593,385 →
Application:
16/418,204 →
Pam-4 Calibration
Phase Rotator Non-Linearity Reduction
Symbol-Rate Phase Detector for Multi-PAM Receiver
Receiver/Transmitter Co-Calibration of Voltage Levels in Pulse Amplitude Modulation Links
Phase-Locked Loop with Phase Information Multiplication
Adjustment of Multi-Phase Clock System
Signal Receiver with Skew-Tolerant Strobe Gating
Patent:
10,891,996 →
Application:
16/800,215 →
Transmit Driver Architecture
Edge Enhancement for Signal Transmitter
Symbol-Rate Phase Detector for Multi-PAM Receiver
Area Efficient Method to Enhance Io Bandwidth by Splitting Driver/Termination and Esd Circuits Across an Inductor
Application:
16/860,435 →
Fragmented Periodic Timing Calibration
Patent:
11,449,439 →
Application:
16/934,008 →
High-Bandwidth Signal Driver/Receiver
Patent:
11,831,153 →
Application:
16/940,679 →
Serializing and Deserializing Stage Testing
Receiver Training of Reference Voltage and Equalizer Coefficients
Serial-Link Receiver Using Time-Interleaved Discrete Time Gain
Efficient Storage of Error Correcting Code Information
Methods and Circuits for Decision-Feedback Equalization Using Compensated Decision Regions
Pam-4 Calibration
Phase Rotator Non-Linearity Reduction
Pattern Detection Based Parameter Adaptation
Receiver/Transmitter Co-Calibration of Voltage Levels in Pulse Amplitude Modulation Links
Signal Receiver with Skew-Tolerant Strobe Gating
Patent:
11,386,941 →
Application:
17/117,411 →
Dual Loop Sar Adc with Process Driven Architecture
Low-Noise Differential-Output Capacitor Dac
Ctle Adaptation Based on Statistical Analysis
Edge Enhancement for Signal Transmitter
Methods and Circuits for Decision-Feedback Equalization with Early High-Order-Symbol Detection
Offset Calibration for Successive Approximation Register Analog to Digital Converter
Multi-Stage Equalizer for Inter-Symbol Interference Cancellation
Direct-Switching H-Bridge Current-Mode Drivers
Circuit and Method to Set Delay Between Two Periodic Signals with Unknown Phase Relationship
Live Offset Cancellation of the Decision Feedback Equalization Data Slicers
Symbol-Rate Phase Detector for Multi-PAM Receiver
Baud-Rate Clock Recovery Lock Point Control
Memory Interface Training
Receiver Training of Reference Voltage and Equalizer Coefficients
Serial-Link Receiver Using Time-Interleaved Discrete Time Gain
Matched Digital-to-Analog Converters
Transmit Driver Architecture
Back-Gate Biasing of Clock Trees Using a Reference Generator
Circuits and Methods for Detecting and Unlocking Edge-Phase Lock
Comparator Set-Reset Latch Circuit and Method for Capacitively Storing Bits
Application:
17/535,776 →
Publication:
US 2022/0166413
Ctle Adaptation Based on Statistical Analysis
Circuit and Method to Set Delay Between Two Periodic Signals with Unknown Phase Relationship
Memory Interface Mapping
Adjustment of Multi-Phase Clock System
Receiver/Transmitter Co-Calibration of Voltage Levels in Pulse Amplitude Modulation Links
Extended-Burst Write Training
Patent:
12,119,080 →
Application:
17/717,419 →
Methods and Circuits for Reducing Clock Jitter
Offset Calibration for Successive Approximation Register Analog to Digital Converter
Serializing and Deserializing Stage Testing
Signal Receiver with Skew-Tolerant Strobe Gating
Patent:
11,749,323 →
Application:
17/845,034 →
Methods and Circuits for Decision-Feedback Equalization with Early High-Order-Symbol Detection
Methods and Circuits for Decision-Feedback Equalization Using Compensated Decision Regions
Edge Enhancement for Signal Transmitter
Low Power Current Mode Logic
Patent:
11,831,315 →
Application:
17/875,608 →
Read Eye Training
Fragmented Periodic Timing Calibration
Multi-Stage Equalizer for Inter-Symbol Interference Cancellation
Matched Digital-to-Analog Converters
Baud-Rate Clock Recovery Lock Point Control
Application:
18/092,561 →
Publication:
US 2023/0254106
Pattern Detection Based Parameter Adaptation
Efficient Storage of Error Correcting Code Information
Live Offset Cancellation of the Decision Feedback Equalization Data Slicers
Signaling Compression and Decompression Associated with a Partially Unrolled Decision Feedback Equalizer (Dfe)
Low Jitter Clock Multiplier Circuit and Method with Arbitary Frequency Acquisition
Circuit and Method to Set Delay Between Two Periodic Signals with Unknown Phase Relationship
Duty-cycle correction circuit
Application:
60/571,733 →
Look-ahead TAG ID Generation for PCI Express Using a Two-deep FIFO, and a Prefetch Register that Guarantees Unique TAG Generation, and Improves Performance.
Application:
60/595,740 →
System and method for jitter control
Application:
60/644,994 →
Analog Convertor With Switched-Capacitor Reset Architecture
Application:
60/744,314 →
Serializer Deserializer
Application:
60/868,137 →
Decision Feedback Equalizer and Transceiver
Application:
61/382,476 →
High-Speed Sst Transmit Driver
Application:
61/533,571 →
Signal Receiver with Skew-Tolerant Strobe Gating
Application:
62/492,408 →
High-Resolution Digitally Controlled Delay Line
Application:
62/520,725 →
Receiver/Transmitter Co-Calibration of Voltage Levels in Pulse Amplitude Modulation Links
Application:
62/542,149 →
Method to Improve Front End Circuit Linearity by Using Discrete Time Gain
Application:
62/659,456 →
Ecc Configuration for Dual Channel Dram
Application:
62/670,582 →
Pam-4 Calibration
Application:
62/688,687 →
Serializing and Deserializing Stage Testing
Application:
62/690,222 →
Phase Rotator Non-Linearity Reduction
Application:
62/690,833 →
Sequential Decision Feedback Equalization
Application:
62/693,260 →
Baud rate pre-computed MMSE phase detection with local skew and global frequency locking
Application:
62/693,271 →
Multi-Comparator SAR Offset Calibration
Application:
62/714,538 →
Efficient Storage of Error Correcting Code Information
Application:
62/720,977 →
Direct-Switching H-Bridge Current-Mode Drivers
Application:
62/727,360 →
Serial-Link Receiver Using Time-Interleaved Discrete Time Gain
Application:
62/727,365 →
Methods and Circuits for Decision-Feedback Equalization with Early High-Order-Symbol Detection
Application:
62/749,869 →
Phase-Locked Loop with Phase Information Multiplication
Application:
62/755,624 →
Sequence decision feedback equalizer
Application:
62/765,109 →
Offset Calibration for Successive Approximation Register Analog to Digital Converter
Application:
62/771,519 →
Multi-Stage Equalizer for Inter-Symbol Interference Cancellation
Application:
62/778,622 →
Live Offset Cancellation of the Decision Feedback Equalization Data Slicers
Application:
62/778,734 →
Adjustment of Multi-Phase Clock System
Application:
62/781,974 →
Transmit Driver Architecture
Application:
62/814,465 →
Edge Enhancement for Signal Transmitter
Application:
62/819,331 →
Symbol-Rate Phase Detector for Multi-PAM Receiver
Application:
62/831,618 →
Area efficient method to enhance the IO Bandwidth by splitting driver/termination and ESD circuits across an inductor
Application:
62/842,659 →
Fragmented Periodic Timing Calibration
Application:
62/878,657 →
Receiver Training of Reference Voltage and Equalizer Coefficients
Application:
62/904,598 →
Pattern Detection Based Parameter Adaptation
Application:
62/947,075 →
Dual Loop Sar Adc with Process Driven Architecture
Application:
62/965,723 →
Low-Noise Differential-Output Capacitor Dac
Application:
62/975,099 →
Ctle Adaptation Based on Statistical Analysis
Application:
62/985,016 →
Baud-Rate Clock Recovery Lock Point Control
Application:
63/036,003 →
Memory Interface Training
Application:
63/065,115 →
On-Die Pwm Reference Voltage Generation for Matched Sampling Levels
Application:
63/074,883 →
Back-Gate Biasing of Clock Trees Using a Reference Generator
Application:
63/114,466 →
Matched Digital-to-Analog Converters
Application:
63/115,194 →
Low Jitter Clock Multiplier Circuit and Method with Arbitary Frequency Acquisition
Application:
63/118,714 →
Comparator Set-Reset Latch Circuit and Method for Capacitively Storing Bits
Application:
63/118,717 →
Circuits and Methods for Detecting and Unlocking Edge-Phase Lock
Application:
63/123,041 →
Memory Interface Mapping
Application:
63/150,245 →
Methods and Circuits for Reducing Clock Jitter
Application:
63/174,093 →
Extended-Burst Write Training
Application:
63/176,796 →
Low Power Current Mode Logic
Application:
63/228,696 →
Read Eye Training
Application:
63/231,972 →
Signaling Compression and Decompression Associated with a Partially Unrolled Decision Feedback Equalizer (Dfe)
Application:
63/339,387 →
Control Signal Training
Application:
63/352,068 →
Methods and Circuits for Inner-Eye Timing Center Detection and Clock Phase Alignment
Application:
63/431,549 →
Oscillator Amplitude Calibration
Application:
63/432,185 →
Select Signal Duty Cycle Adjustment
Application:
63/433,066 →
Signal Receiver with Adaptive Strobe Gating and Reduced Power Datapath Architecture
Application:
63/442,416 →
Clock Gating
Application:
63/452,827 →
Common Mode Shifting of Single-Ended Signals Based on Linearity Analysis
Application:
63/502,801 →
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 5, 2007
From: REZAYEE, AFSHIN; MARTIN, KEN; BUCHWALD, AARON
To: SNOWBUSH, INC.
Reel/Frame 019575/0287 →
Assignment of Assignor's Interest
Jan 7, 2008
From: SNOWBUSH INC.
To: GENNUM CORPORATION
Reel/Frame 020325/0366 →
Assignment of Assignor's Interest
Feb 11, 2008
From: MARTIN, KENNETH W.; ROGERS, JONATHAN E.; PIALIS, TONY; RAMEZANI, MEHRDAD
To: SNOWBUSH INC.
Reel/Frame 020508/0321 →
Assignment of Assignor's Interest
Dec 23, 2008
From: MISHRA, KISHORE KUMAR; MOHANTY, PURNA
To: ASIC ARCHITECT, INC.
Reel/Frame 022025/0575 →
Assignment of Assignor's Interest
Apr 26, 2012
From: ABDALLA, MOHAMED; CASSAN, DAVID; VAN IERSSEL, MARCUS; HOLDENRIED, CHRIS
To: GENNUM CORPORATION
Reel/Frame 028111/0240 →
Assignment of Assignor's Interest
Apr 26, 2012
From: REZAYEE, AFSHIN
To: GENNUM CORPORATION
Reel/Frame 028111/0433 →
Merger
Jun 25, 2012
From: GENNUM CORPORATION
To: SEMTECH CANADA INC.
Reel/Frame 028436/0762 →
Assignment of Assignor's Interest
Oct 8, 2012
From: GENNUM US LIMITED (F/K/A/ ASIC ARCHITECT, INC.)
To: SEMTECH CORPORATION
Reel/Frame 029092/0200 →
Assignment of Assignor's Interest
Oct 24, 2012
From: FARZAN, KAMRAN; RAMEZANI, MEHRDAD; CASSAN, DAVID; MCLAREN, ANGUS
To: SEMTECH CANADA, INC.
Reel/Frame 029180/0175 →
Grant of Security Interest
Dec 18, 2012
From: SEMTECH CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 029495/0347 →
Release of Security Interest
May 2, 2013
From: JEFFERIES FINANCE LLC
To: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.
Reel/Frame 030341/0059 →
Security Agreement
May 2, 2013
From: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 030341/0099 →
Change of Name
Jun 7, 2013
From: SEMTECH CANADA INC.
To: SEMTECH CANADA CORPORATION
Reel/Frame 030575/0052 →
Change of Name
Jun 7, 2013
From: GENNUM CORPORATION
To: SEMTECH CANADA INC.
Reel/Frame 030565/0874 →
Patent Security Agreement
May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Change of Name
Nov 11, 2014
From: SEMTECH CANADA INC
To: SEMTECH CANADA CORPORATION
Reel/Frame 034206/0011 →
Assignment of Assignor's Interest
Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
Assignment of Assignor's Interest
Sep 30, 2015
From: RAMEZANI, MEHRDAD; CASSAN, DAVID J.; HOLDENRIED, CHRISTOPHER D.; VAN IERSSEL, MARCUS
To: SEMTECH CORPORATION
Reel/Frame 036698/0307 →
Security Interest
Dec 14, 2015
From: SEMTECH CORPORATION
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 037284/0745 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031)
Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
Patent Security Agreement
Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
Partial Release of Security Interest in Patents
Aug 5, 2016
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: SEMTECH CORPORATION; SEMTECH NEW YORK CORPORATION; SIERRA MONOLITHICS, INC.
Reel/Frame 039595/0388 →
Partial Release of Security Interest in Patents
Aug 5, 2016
From: HSBC BANK USA, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: SEMTECH CORPORATION
Reel/Frame 039595/0371 →
Assignment of Assignor's Interest
Aug 15, 2016
From: SEMTECH CORPORATION
To: RAMBUS INC
Reel/Frame 039435/0798 →
Assignment of Assignor's Interest
Aug 15, 2016
From: SEMTECH CANADA INC.
To: RAMBUS CANADA INC
Reel/Frame 039436/0152 →