Signal receiver with skew-tolerant strobe gating
A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.
1. A method of operation within an integrated-circuit component, the method comprising:
receiving, via an external timing signal link, a timing-strobe signal having (i) a sequence of data-timing transitions preceded by a preamble interval and succeeded by a postamble interval, and (ii) a time-varying phase relative to an internal timing domain of the integrated-circuit component;
detecting a low state of the timing-strobe signal that precedes the initial one of the data-timing transitions and asserting a strobe-gate signal in response; and
deasserting the strobe-gate signal at a deterministic time relative to a final one of the data-timing transitions, despite the time-varying phase of the timing-strobe signal relative to the internal timing domain of the integrated-circuit component.
2. The method of claim 1 wherein detecting the low state of the timing-strobe signal comprises detecting a low state of the timing-strobe signal that transpires within the preamble interval.
3. The method of claim 1 further comprising asserting an input-gate signal over a predetermined assertion interval having a fixed phase relative to the internal timing domain, the predetermined interval spanning at least a portion of the low state of the timing-strobe despite timing skew between the timing-strobe signal and the internal timing domain within a predetermined skew tolerance.
4. The method of claim 3 wherein detecting the low state of the timing-strobe signal and asserting the strobe-gate signal in response comprises asserting the strobe-gate signal in response to concurrence between the low-state of the timing-strobe signal and the input-gate signal assertion interval.
5. The method of claim 1 further comprising logically combining the timing-strobe signal and the strobe-gate signal to generate a sample-timing signal having a sequence of data-timing transitions that correspond to the data-timing transitions in the timing-strobe signal, but lacking transitions present in the preamble and postamble intervals of the timing-strobe signal.
6. The method of claim 5 wherein deasserting the strobe-gate signal at a deterministic time relative to a final one of the data-timing transitions comprises deasserting the strobe-gate signal in response to a final one of the data-timing transitions in the sample-timing signal.
7. The method of claim 6 further comprising asserting an input-gate signal over a predetermined assertion interval having a fixed phase relative to the internal timing domain, the predetermined interval spanning a penultimate falling one of the data-timing transitions within the sample-timing signal and concluding prior to a final falling one of the data-timing transitions within the sample-timing signal, despite timing skew between the timing-strobe signal and the internal timing domain within a predetermined skew tolerance.
8. The method of claim 7 wherein deasserting the strobe-gate signal in response to the final one of the data-timing transitions comprises sampling the input-gate signal in response to at least the final falling one of the data-timing transitions within the sample-timing signal.
9. The method of claim 5 further comprising:
receiving a data signal via an external data signal link; and
sampling the data signal at times indicated by the data-timing transitions in the sample-timing signal to recover a sequence of data values conveyed in the data signal.
10. The method of claim 9 wherein receiving the timing-strobe signal via the external timing link and the data signal via the external data signal link comprises receiving the timing-strobe signal and the data signal from a memory component.
11. An integrated-circuit component comprising:
a timing signal input to receive, via an external timing signal link, a timing-strobe signal having (i) a sequence of data-timing transitions preceded by a preamble interval and succeeded by a postamble interval, and (ii) a time-varying phase relative to an internal timing domain of the integrated-circuit component;
strobe gating circuitry to:
detect a low state of the timing-strobe signal that precedes the initial one of the data-timing transitions and assert a strobe-gate signal in response; and
deassert the strobe-gate signal at a deterministic time relative to a final one of the data-timing transitions, despite the time-varying phase of the timing-strobe signal relative to the internal timing domain of the integrated-circuit component.
12. The integrated-circuit component of claim 11 wherein the strobe gating circuitry to detect the low state of the timing-strobe signal comprises circuitry to detect a low state of the timing-strobe signal that transpires within the preamble interval.
13. The integrated-circuit component of claim 11 further comprising control circuitry to assert an input-gate signal over a predetermined assertion interval having a fixed phase relative to the internal timing domain, the predetermined interval spanning at least a portion of the low state of the timing-strobe despite timing skew between the timing-strobe signal and the internal timing domain within a predetermined skew tolerance.
14. The integrated-circuit component of claim 13 wherein the strobe gating circuitry to detect the low state of the timing-strobe signal and assert the strobe-gate signal in response comprises circuitry to assert the strobe-gate signal in response to concurrence between the low-state of the timing-strobe signal and the input-gate signal assertion interval.
15. The integrated-circuit component of claim 11 further comprising logic circuitry to logically combine the timing-strobe signal and the strobe-gate signal to generate a sample-timing signal having a sequence of data-timing transitions that correspond to the data-timing transitions in the timing-strobe signal, but lacking transitions present in the preamble and postamble intervals of the timing-strobe signal.
16. The integrated-circuit component of claim 15 wherein the strobe gating circuitry to deassert the strobe-gate signal at a deterministic time relative to a final one of the data-timing transitions comprises circuitry to deassert the strobe-gate signal in response to a final one of the data-timing transitions in the sample-timing signal.
17. The integrated-circuit component of claim 16 further comprising control circuitry to assert an input-gate signal over a predetermined assertion interval having a fixed phase relative to the internal timing domain, the predetermined interval spanning a penultimate falling one of the data-timing transitions within the sample-timing signal and concluding prior to a final falling one of the data-timing transitions within the sample-timing signal, despite timing skew between the timing-strobe signal and the internal timing domain within a predetermined skew tolerance.
18. The integrated-circuit component of claim 17 wherein the strobe gating circuitry to deassert the strobe-gate signal in response to the final one of the data-timing transitions comprises circuitry to sample the input-gate signal in response to at least the final falling one of the data-timing transitions within the sample-timing signal.
19. The integrated-circuit component of claim 15 further comprising:
a data signal input to receive a data signal via an external data signal link; and
data sampling circuitry to sample the data signal at times indicated by the data-timing transitions in the sample-timing signal to recover a sequence of data values conveyed in the data signal.
20. An integrated circuit component comprising:
a timing signal input to receive, via an external timing signal link, a timing-strobe signal having (i) a sequence of data-timing transitions preceded by a preamble interval and succeeded by a postamble interval, and (ii) a time-varying phase relative to an internal timing domain of the integrated-circuit component;
means for detecting a low state of the timing-strobe signal that precedes the initial one of the data-timing transitions and asserting a strobe-gate signal in response; and
means for deasserting the strobe-gate signal at a deterministic time relative to a final one of the data-timing transitions, despite the time-varying phase of the timing-strobe signal relative to the internal timing domain of the integrated-circuit component.