Deserialized dual-loop clock radio and data recovery circuit
View Patent ↗A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.
1. A clock and data recovery circuit (CDR), comprising:
a digitally controlled oscillator (DCO), having a frequency control input and a delay control input:
a data sampler coupled to receive a clock signal from the DCO;
a deserializer including an input coupled to an output of the data sampler;
a first phase detector coupled to receive a first data output of the deserializer and provide a delay control signal to the frequency control input of the DCO;
a second phase detector coupled to a second data output of the deserializer; and
an accumulator coupled to receive between an output of the second phase detector and to provide a frequency control signal to the frequency control input of the DCO.
2. The CDR of claim 1 , further including a frequency lock detection block coupled to an output of the accumulator.
3. The CDR of claim 1 , further including an eye monitor coupled to an input of the data sampler.
4. The CDR of claim 1 , further including an edge mute signal coupled to the deserializer.
5. A clock and data recovery circuit (CDR), comprising:
a clock generator;
a data sampler coupled to receive a clock signal from the clock generator;
a deserializer coupled to an output of the data sampler;
a first phase detector coupled between a first output of the deserializer and a first input of the clock generator and configured to control a delay of the clock generator; and
a second phase detector coupled between a second output of the deserializer and a second input of the clock generator and configured to control a frequency of the clock generator.
6. The CDR of claim 5 , wherein the deserializer includes:
a first shift register coupled to the first output of the deserializer; and
a second shift register coupled to the second output of the deserializer, wherein a bit-width of the second shift register is different than a bit-width of the first shift register.
7. The CDR of claim 6 , wherein the first shift register and second shift register are coupled in series.
8. The CDR of claim 5 , further including an accumulator coupled between the second phase detector and the clock generator.
9. The CDR of claim 5 , further including a frequency lock detection block coupled between the second phase detector and the clock generator.
10. The CDR of claim 5 , further including a clock divider coupled between the clock generator and the data sampler.
11. The CDR of claim 5 , further including an edge mute signal coupled to the deserializer.
12. The CDR of claim 5 , wherein the data sampler includes a decision feedback equalization circuit.
13. A clock and data recovery circuit (CDR), comprising:
a clock generator having a controllable delay and a controllable frequency;
a data sampler;
a deserializer coupled to an output of the data sampler;
a proportional feedback path including a first phase detector coupled to receive a first set of data from the deserializer and to, based on the first set of data, adjust the controllable delay of the clock generator; and
an integral feedback path including a second phase detector coupled to receive a second set of data from the deserializer and to, based on the second set of data, adjust the controllable frequency of the clock generator.
14. The CDR of claim 13 , further including a phase interpolator coupled to receive a first clock signal from the clock generator and to provide a second clock signal to the data sampler.
15. The CDR of claim 13 , further including an accumulator coupled to an output of the second phase detector.
16. The CDR of claim 13 , wherein the data sampler includes a decision feedback equalization circuit.
17. The CDR of claim 13 , wherein the second set of data includes a plurality of parallel data bits.
18. The CDR of claim 13 , further including an edge mute signal coupled to an input of the deserializer.
19. A method of a clock and data recovery (CDR), comprising:
providing a data sampler with serial data;
deserializing an output of the data sampler;
receiving, at a first phase detector a first set of data from the deserializer;
receiving, at coupling a second phase detector a second set of data from the deserializer;
based on a delay error signal generated by the first phase detector using the first set of data, adjusting the delay of a clock generator; and,
based on a frequency error signal generated by the second phase detector using the second set of data, adjusting the frequency of the clock generator.
20. The method of claim 19 , further including providing a clock signal to the data sampler using a phase interpolator.
21. The method of claim 20 , further including calibrating the phase interpolator by providing the clock signal as a data input to the data sampler.