Signal receiver with skew-tolerant strobe gating
A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.
1. A method of operation within an integrated-circuit component having a data input to receive a sequence of data values and a timing input, the method comprising:
receiving, via the timing input, a first timing signal having a sequence of data-timing transitions corresponding to the sequence of data values;
asserting a control signal prior to an initial one of the data-timing transitions and deasserting the control signal prior to a trailing one of the data-timing transitions;
asserting a gating signal in response to detecting a predetermined state of the first timing signal during assertion of the control signal; and
deasserting the gating signal after deassertion of the control signal and in response to the trailing one of the data-timing transitions.
2. The method of claim 1 wherein asserting the control signal prior to the initial one of the data-timing transitions and deasserting the control signal prior to the trailing one of the data-timing transitions comprises generating, as the control signal, a control pulse that commences prior to the initial one of the data-timing transitions and has a pulse width nominally equal to a time period between the initial one of the data-timing transitions and the trailing one of the data-timing transitions.
3. The method of claim 1 wherein asserting and deasserting the control signal comprises asserting and deasserting the control signal synchronously with respect to a clock signal having a time-varying phase offset relative to the first timing signal.
4. The method of claim 3 wherein the time-varying phase offset ranges between a maximum phase offset and a minimum phase offset that are separated by twice the period of the clock signal.
5. The method of claim 4 wherein the time-varying phase offset ranges non-inclusively between the maximum and minimum phase offsets.
6. The method of claim 1 wherein the first timing signal is characterized by a preamble having a predetermined duration, and wherein asserting the control signal prior to the initial one of the data-timing transitions comprises asserting the control signal at a nominal midpoint of the predetermined duration of the preamble.
7. The method of claim 6 wherein asserting the control signal at a nominal midpoint of the predetermined duration of the preamble comprises asserting the control signal in response to a transition of a clock signal having a time-varying phase offset relative to the first timing signal such that assertion of the control signal at the nominal midpoint of the predetermined duration of the preamble may result in assertion of the control signal at any time after commencement of the preamble and prior to conclusion of the preamble.
8. The method of claim 1 wherein deasserting the control signal comprises deasserting the control signal in response to a transition of a clock signal having a time-varying phase offset relative to the first timing signal such that the control signal is deasserted, for at least one permissible sub-range of the time-varying phase offset, prior to one of the data-timing transitions that precedes the trailing one of the data-timing transitions.
9. The method of claim 8 wherein the one of the data-timing transitions that precedes the trailing one of the data-timing transitions comprises a transition of the first timing signal from a first voltage level to a second voltage level, and wherein deasserting the gating signal after deassertion of the control signal and in response to the trailing one of the data-timing transitions comprises deasserting the gating signal in response to a transition of the first timing signal from the second voltage level to the first voltage level that occurs after deassertion of the control signal such that, when the control signal is deasserted while a phase difference between the clock signal and the first timing signal is within the at least one permissible sub-range of the time-varying phase offset, the gating signal remains asserted before and after the one of the data-timing transitions that precedes the trailing one of the data-timing transitions.
10. The method of claim 1 wherein the first timing signal is characterized by a preamble transition that precedes the data-timing transitions and a postamble transition that follows the data-timing transitions, the method further comprising logically combining the first timing signal and the gating signal to generate a second timing signal that (i) lacks transitions corresponding to the preamble and postamble transitions of the first timing signal and (ii) includes a sequence of data-timing transitions that correspond to the data-timing transitions of the first timing signal.
11. An integrated-circuit component comprising:
a data input to receive a sequence of data values;
a timing input to receive a first timing signal having a sequence of data-timing transitions corresponding to the sequence of data values; and
gating circuitry to:
assert a control signal prior to an initial one of the data-timing transitions,
deassert the control signal prior to a trailing one of the data-timing transitions,
assert a gating signal in response to detecting a predetermined state of the first timing signal during assertion of the control signal, and
deassert the gating signal after deassertion of the control signal and in response to the trailing one of the data-timing transitions.
12. The integrated-circuit component of claim 11 wherein the gating circuitry to assert the control signal prior to the initial one of the data-timing transitions and to deassert the control signal prior to the trailing one of the data-timing transitions comprises circuitry to generate, as the control signal, a control pulse that commences prior to the initial one of the data-timing transitions and has a pulse width nominally equal to a time period between the initial one of the data-timing transitions and the trailing one of the data-timing transitions.
13. The integrated-circuit component of claim 11 wherein the gating circuitry to assert and deassert the control signal comprises circuitry to assert and deassert the control signal synchronously with respect to a clock signal having a time-varying phase offset relative to the first timing signal.
14. The integrated-circuit component of claim 13 wherein the time-varying phase offset ranges between a maximum permissible phase offset and a minimum permissible phase offset that are separated by twice the period of the clock signal.
15. The integrated-circuit component of claim 11 wherein the first timing signal is characterized by a preamble having a predetermined duration, and wherein the gating circuitry to assert the control signal prior to the initial one of the data-timing transitions comprises circuitry to assert the control signal at a nominal midpoint of the predetermined duration of the preamble.
16. The integrated-circuit component of claim 15 wherein the circuitry to assert the control signal at the nominal midpoint of the predetermined duration of the preamble comprises circuitry to assert the control signal in response to a transition of a clock signal having a time-varying phase offset relative to the first timing signal such that assertion of the control signal at the nominal midpoint of the predetermined duration of the preamble may result in assertion of the control signal at any time after commencement of the preamble and prior to conclusion of the preamble.
17. The integrated-circuit component of claim 11 wherein the gating circuitry to deassert the control signal comprises circuitry to deassert the control signal in response to a transition of a clock signal having a time-varying phase offset relative to the first timing signal such that the control signal is deasserted, for at least one permissible sub-range of the time-varying phase offset, prior to one of the data-timing transitions that precedes the trailing one of the data-timing transitions.
18. The integrated-circuit component of claim 17 wherein the one of the data-timing transitions that precedes the trailing one of the data-timing transitions comprises a transition of the first timing signal from a first voltage level to a second voltage level, and wherein the gating circuitry to deassert the gating signal after deassertion of the control signal and in response to the trailing one of the data-timing transitions comprises circuitry to deassert the gating signal in response to a transition of the first timing signal from the second voltage level to the first voltage level that occurs after deassertion of the control signal such that, when the control signal is deasserted while a phase difference between the clock signal and the first timing signal is within the at least one permissible sub-range of the time-varying phase offset, the gating signal remains asserted before and after the one of the data-timing transitions that precedes the trailing one of the data-timing transitions.
19. The integrated-circuit component of claim 11 wherein the first timing signal is characterized by a preamble transition that precedes the data-timing transitions and a postamble transition that follows the data-timing transitions, the integrated-circuit component further comprising logic circuitry to logically combine the first timing signal and the gating signal to generate a second timing signal that (i) lacks transitions corresponding to the preamble and postamble transitions of the first timing signal and (ii) includes a sequence of data-timing transitions that correspond to the data-timing transitions of the first timing signal.
20. An integrated-circuit component comprising:
a data input to receive a sequence of data values;
a timing input to receive a first timing signal having a sequence of data-timing transitions corresponding to the sequence of data values; and
means for:
asserting a control signal prior to an initial one of the data-timing transitions,
deasserting the control signal prior to a trailing one of the data-timing transitions,
asserting a gating signal in response to detecting a predetermined state of the first timing signal during assertion of the control signal, and
deasserting the gating signal after deassertion of the control signal and in response to the trailing one of the data-timing transitions.