Adjustment of multi-phase clock system
Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.
1. An integrated circuit, comprising:
first circuitry to output a first timing reference signal;
second circuitry to output a second timing reference signal;
third circuitry to output a third timing reference signal;
relative timing difference circuitry to produce a first relative difference indicator based on a first timing between the first timing reference signal and the second timing reference signal, and to produce a second relative difference indicator based on a second timing between the second timing reference signal and the third timing reference signal, and to produce a third relative difference indicator based on a third timing between the third timing reference signal and the first timing reference signal; and
timing adjustment circuitry, coupled to the first circuitry, the second circuitry, and the third circuitry, to adjust, based on a rank of the first relative difference indicator, the second relative difference indicator, and the third relative difference indicator, adjust a timing of at least one of the first timing reference signal, the second timing reference signal, and the third timing reference signal.
2. The integrated circuit of claim 1 , wherein the first relative difference indicator, the second relative difference indicator, and the third relative difference indicator correspond to whether respective time differences between respective pairs of signals is greater than, or less than, each other.
3. The integrated circuit of claim 2 , further comprising:
timing difference ranker circuitry to sort the first timing, the second timing, and the third timing according to magnitudes as indicated by the first relative difference indicator, the second relative difference indicator, and the third relative difference indicator.
4. The integrated circuit of claim 3 , further comprising:
a hold circuit to temporarily hold the first relative difference indicator, the second relative difference indicator, and the third relative difference indicator.
5. The integrated circuit of claim 4 , wherein the timing difference ranker circuitry compares a held version of the first relative difference indicator to the second relative difference indicator, and compares a held version of the second relative difference indicator to the third relative difference indicator, and compares a held version of the third relative difference indicator to the first relative difference indicator.
6. The integrated circuit of claim 5 , wherein the hold circuit includes an analog sample-and-hold circuit.
7. The integrated circuit of claim 1 , further comprising:
a multiplexer circuit to provide the first timing reference signal, the second timing reference signal, and the third timing reference signal to relative timing difference circuitry.
8. The integrated circuit of claim 7 , wherein the multiplexer circuit concurrently provides at least two of the first timing reference signal, the second timing reference signal, and the third timing reference signal to relative timing difference circuitry.
9. An integrated circuit, comprising:
first circuitry to output a first timing reference signal;
second circuitry to output a second timing reference signal;
third circuitry to output a third timing reference signal;
time difference measurement circuitry to generate a set of at least three indicators that correspond to differences in time differences between pairs of the first timing reference signal, the second timing reference signal, and the third timing reference signal; and
adjustment circuitry coupled to the first circuitry, the second circuitry, and the third circuitry to, based on the set of at least three indicators, adjust a timing difference between, at least the first timing reference signal and the second timing reference signal.
10. The integrated circuit of claim 9 , wherein each of the set of at least three indicators is associated with respective pairs of the first timing reference signal, the second timing reference signal, and the third timing reference signal, and each of the set of at least three indicators correspond to whether a first time difference between signals of a first one of a respective signal pair is greater than, or less, than a second time difference between signals of a second signal pair.
11. The integrated circuit of claim 10 , wherein the adjustment circuitry is to sort respective signal pairs according to the differences in time differences between pairs of the first timing reference signal, the second timing reference signal, and the third timing reference signal.
12. The integrated circuit of claim 9 , wherein the time difference measurement circuitry comprises:
time difference capture circuitry to generate a first indicator of a time difference between a first pair of signals and to generate a second indicator of a time difference between a second pair of signals; and
time difference compare circuitry to generate a relative difference indicator that corresponds to whether of the first indicator is associated with a one of a greater or lesser time difference than the second indicator.
13. The integrated circuit of claim 12 , wherein the time difference measurement circuitry further comprises:
time difference indicator storage circuitry to hold the first indicator while the second indicator is generated and to provide the first indicator to the time difference compare circuitry.
14. The integrated circuit of claim 13 , wherein the time difference indicator storage circuitry includes a sample-and-hold circuit.
15. The integrated circuit of claim 14 , further comprising:
a multiplexer circuit to select a first pair of signals; and
a time difference indicator circuit to provide a first pulse corresponding to the time difference between the first pair of signals to the time difference capture circuitry.
16. A method of operating an integrated circuit, comprising:
generating a set of at least three indicators that correspond to relative differences in time differences between a set of at least three signal pairs selected from a set of signals that includes at least three signals;
ranking each of the time differences between each of the set of at least three signal pairs based on the set of at least three indicators; and
based on the ranking, adjusting a timing of at least one of the set of signals.
17. The method of claim 16 , wherein generating the set of at least three indicators further comprises:
storing a version of a first indicator;
generating a second indicator of a second time difference between a third signal and a fourth signal of a second signal pair; and
comparing the version of the first indicator to the second indicator to produce one of the set of at least three indicators.
18. The method of claim 17 , wherein each of the set of at least three indicators corresponds to which signal pair of a pair of signal pairs has a greater time difference between members of said signal pair.
19. The method of claim 16 , wherein generating the set of at least three indicators further comprises:
generating a first indicator of a first time difference between a first signal and a second signal of a first signal pair.
20. The method of claim 18 , wherein generating the set of at least three indicators further comprises:
generating a second indicator of a second time difference between a third signal and a fourth signal of a second signal pair; and
comparing the first indicator to the second indicator to produce one of the set of at least three indicators.