Deserialized dual-loop clock radio and data recovery circuit
A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.
1. A clock and data recovery circuit (CDR), comprising:
an oscillator having at least a frequency control input and a delay control input;
a data sampler coupled to receive a clock signal from the oscillator;
a register that includes an input to receive an output of the data sampler;
a first phase detector coupled to receive a first at least one data value stored by the register and to provide a delay control signal to the delay control input of the oscillator;
a second phase detector coupled to receive a second at least one data value stored by the register; and
an integrator coupled to receive an output of the second phase detector and to provide a frequency control signal to the frequency control input of the oscillator.
2. The CDR of claim 1 , further comprising circuitry to discard samples output by the data sampler.
3. The CDR of claim 2 , wherein the circuitry to discard samples prevents samples from being stored in the register.
4. The CDR of claim 1 , further comprising an eye monitor coupled to an input of the data sampler.
5. The CDR of claim 1 , further comprising frequency lock detection circuitry coupled to an output of the integrator.
6. The CDR of claim 1 , further comprising a phase interpolator coupled between the oscillator and the data sampler.
7. The CDR of claim 6 , further comprising calibration circuitry to shift a plurality of clocks output by the phase interpolator relative to each other.
8. A clock and data recovery circuit (CDR), comprising:
a clock generator;
a data sampler coupled to receive a clock signal based on a clock signal generated by the clock generator;
a register coupled to receive output values sampled by the data sampler;
a first phase detector coupled to receive a first at least one output value stored by the register and based on the first at least one output value control a delay of the clock generator;
a second phase detector coupled to receive a second at least one output value stored by the register and based on the first at least one output value control a frequency of the clock generator.
9. The CDR of claim 8 , wherein the first at least one output value and the second at least one output value have different numbers of bits.
10. The CDR of claim 8 , wherein the register comprises a shift register.
11. The CDR of claim 8 , wherein the register comprises a first shift register to store in-phase samples and a second shift register to store edge samples.
12. The CDR of claim 8 , further comprising:
an integrator to receive an output of the second phase detector and to produce a frequency control signal that controls the frequency of the clock generator.
13. The CDR of claim 8 , further comprising a phase interpolator coupled between the oscillator and the data sampler.
14. The CDR of claim 13 , further comprising calibration circuitry to shift a plurality of clocks output by the phase interpolator relative to each other.
15. A method of clock and data recovery (CDR), comprising:
providing a data sampler with serial data;
storing a plurality of output values sampled by the data sampler in a register;
receiving, by a first phase detector, a first set of data stored by the register;
receiving, by a second phase detector, a second set of data stored by the register;
based on a delay error signal generated by the first phase detector based at least in part of the first set of data, adjust a delay of a clock generator;
based on a frequency error signal generated by the second phase detector based at least in part of the second set of data, adjust a frequency of the clock generator.
16. The method of claim 15 , further comprising:
providing a clock signal from the clock generator to a phase interpolator.
17. The method of claim 15 , further comprising:
providing a plurality of clock signals generated by a phase interpolator to the data sampler.
18. The method of claim 17 , further comprising:
shifting the plurality of clock signals generated by the phase interpolator relative to each other.
19. The method of claim 18 , further comprising:
providing a reference clock signal to the clock generator.
20. The method of claim 19 , wherein the reference clock signal is not used after calibration of the clock generator.