Memory interface mapping
System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information.
1. A memory controller integrated circuit, comprising:
a command/address (CA) interface comprising a first plurality of terminals to communicate a corresponding plurality of CA signals, each of the first plurality of terminals configurable to function as a selectable one of the plurality of CA signals;
a data (DQ) interface comprising a second plurality of terminals to communicate a corresponding plurality of DQ signals, each of the second plurality of terminals configurable to function as a selectable one of the plurality of DQ signals; and
a CA interconnect including a plurality of interconnect mappings, wherein the CA interconnect maps at least one signal terminal to a different signal terminal of the CA interface through the plurality of interconnect mappings.
2. The memory controller integrated circuit of claim 1 , further comprising:
CA interface training circuitry configured to account for a first mapping of each of the first plurality of terminals to respective ones of the plurality of CA signals.
3. The memory controller integrated circuit of claim 2 , wherein the CA interface training circuitry is further configured to account for a second mapping of each of the second plurality of terminals configurable to respective ones of the plurality of DQ signals.
4. The memory controller integrated circuit of claim 1 , further comprising:
error detection code calculation circuitry configured to account for a mapping of each of the second plurality of terminals to respective ones of the plurality of DQ signals.
5. The memory controller integrated circuit of claim 1 , further comprising:
vendor identification reading circuitry configured to account for a mapping of each of the second plurality of terminals to respective ones of the plurality of DQ signals.
6. The memory controller integrated circuit of claim 1 , wherein groups of the second plurality of terminals are configurable to function as selectable groups of the plurality of DQ signals.
7. The memory controller integrated circuit of claim 6 , wherein the groups of the second plurality of terminals and the groups of the plurality of DQ signals are eight bit groups.
8. The memory controller integrated circuit of claim 7 , further comprising:
clock training circuitry configured to account for a mapping of the groups of the second plurality of terminals to respective groups of the plurality of DQ signals.
9. The memory controller integrated circuit of claim 7 , further comprising:
byte masking circuitry configured to account for a mapping of the groups of the second plurality of terminals to respective groups of the plurality of DQ signals.
10. A memory controller, comprising:
a command/address (CA) interface comprising a first plurality of terminals to communicate a corresponding plurality of CA signals;
CA mapping circuitry to configure a first mapping of each of the first plurality of terminals to convey a respective one of the plurality of CA signals;
a data (DQ) interface comprising a second plurality of terminals to communicate a corresponding plurality of DQ signals;
DQ mapping circuitry to configure a second mapping of each of the second plurality of terminals to convey a respective one of the plurality of DQ signals; and
a CA interconnect including a plurality of interconnect mappings, wherein the CA interconnect maps at least one signal terminal to a different signal terminal of the CA interface through the plurality of interconnect mappings.
11. The memory controller of claim 10 , wherein the second mapping maps eight bit groups.
12. The memory controller of claim 11 , further comprising:
clock training circuitry configured to account for the second mapping.
13. The memory controller of claim 12 , further comprising:
byte masking circuitry configured to account for the second mapping.
14. The memory controller of claim 10 , further comprising:
CA interface training circuitry configured to account for the first mapping.
15. The memory controller of claim 14 , wherein the CA interface training circuitry is further configured to account for the second mapping.
16. The memory controller of claim 10 , further comprising: error detect correct (EDC) calculation circuitry configured to account for the second mapping.
17. The memory controller of claim 10 , further comprising:
vendor identification reading circuitry configured to account for the second mapping.
18. A method of operating a memory controller, comprising:
receiving information about a first mapping of connections that relates a plurality of command/address (CA) pins of a CA interface to CA logical functions of a memory device;
receiving information about a second mapping of connections that relates a plurality of data (DQ) pins of a DQ interface to DQ logical bit assignments of the memory device;
configuring first circuitry to reverse the first mapping when transmitting commands to the memory device;
configuring second circuitry to reverse the second mapping to produce unmapped data; and
providing a CA interconnect including a plurality of interconnect mappings, wherein the CA interconnect maps at least one signal terminal to a different signal terminal of the CA interface through the plurality of interconnect mappings.
19. The method of claim 18 , further comprising:
training the CA interface based on the first mapping.
20. The method of claim 18 , further comprising:
training the DQ interface per pin settings based on the second mapping.