Methods and circuits for reducing clock jitter

1. A method comprising:

sampling a sequence of symbols on edges of a clock signal to produce a sequence of data samples, the sequence of data samples exhibiting a first sample pattern and a second sample pattern, the clock signal exhibiting a clock phase and a clock frequency;

generating a phase-error signal responsive to the symbols and the clock signal;

amplifying the phase-error signal by a gain factor to produce a control signal;

adjusting at least one of the clock phase and the clock frequency responsive to the control signal;

sampling at least a subset of the symbols to produce a sequence of error samples;

counting a first number of the error samples correlated with the first sample pattern;

counting a second number of the error samples correlated with the second sample pattern; and

adjusting the gain factor responsive to the first number of the error samples and the second number of the error samples.

2. The method of claim 1 , wherein each symbol in the sequence of symbols represents multiple bits.

3. The method of claim 1 , wherein the first pattern consists of three consecutive symbol levels.

4. The method of claim 1 , wherein adjusting the gain factor comprises writing a gain-factor value to a register.

5. The method of claim 1 , further comprising writing the first number of the error samples to a first register and the second number of the error samples to a second register.

6. The method of claim 5 , further comprising reading the first number of the error samples from the first register, reading the second number of the error samples from the second register, and calculating a new gain factor from the first number and the second number, wherein adjusting the gain factor comprises writing the new gain factor to a third register.

7. A receiver comprising:

an input node to receive an input signal expressing a series of symbols, the series of symbols having a first symbol pattern in which a first pair of adjacent symbols includes a first transition of a first slew rate and a second symbol pattern in which a second pair of adjacent symbols includes a second transition at a second slew rate different from the first slew rate;

a data sampler to produce data samples from the series of symbols, the data sampler to sample the symbols in time to a clock signal;

an error sampler to produce error samples from the series of symbols;

a clock-recovery circuit having a loop filter that exhibits a loop-filter gain, the clock-recovery circuit to recover the clock signal from the data samples and the error samples; and

a jitter detector to detect first jitter associated with the first slew rate and second jitter associated with the second slew rate.

8. The receiver of claim 7 , further comprising loop-gain adaptation logic to adjust the loop-filter gain responsive to the first jitter and the second jitter.

9. The receiver of claim 8 , wherein the data sampler, the error sample, and the clock-recovery circuit are instantiated on an integrated circuit, the integrated circuit further comprising an interface to communicate with at least a portion of the loop-gain adaptation logic instantiated off the integrated circuit.

10. The receiver of claim 8 , the jitter detector to accumulate first instances of the first jitter and second instances of the second jitter, the loop-gain adaptation to adjust the loop-filter gain responsive to a ratio of first instances to the second instances.

11. The receiver of claim 10 , wherein the loop-filter gain comprises proportional gain, the loop-gain adaptation to further adjust an integral gain of the loop filter responsive to the first jitter and the second jitter.

12. The receiver of claim 7 , the jitter detector further comprising a first counter to count instances of the first jitter and a second counter to count instances of the second jitter.

13. The receiver of claim 7 , the jitter detector detecting the first jitter by relating a first pattern of the data samples to the error samples and the second jitter by relating a second pattern of the data samples to the error samples.

14. The receiver of claim 7 , wherein each of the symbols expresses at least two binary bits of data.

15. The receiver of claim 7 , the first slew rate comprising a first change of voltage between the first pair of adjacent symbols and the second slew rate a second change of voltage between the second pair of adjacent symbols and greater than the first change of voltage.

16. A method of controlling a loop gain of a filter on an integrated circuit, the method comprising:

receiving, from the integrated circuit, a first number of slew-rate samples corresponding to a first inter-symbol slew rate;

receiving, from the integrated circuit, a second number of slew-rate samples corresponding to a second inter-symbol slew rate;

calculating a loop-gain adjustment from the first number and the second number;

transmitting the loop-gain adjustment to the integrated circuit; and

correlating the slew-rate samples of the first number of slew-rate samples with first errors and correlating the slew-rate samples of the second number of slew-rate samples with second errors;

wherein calculating the loop-gain adjustment from the first number and the second number comprises taking a ratio of the slew-rate samples correlated with the first errors to the slew-rate samples correlated with the second errors.

17. The method of claim 16 , wherein the receiving of at least one of the first number and the second number comprises reading a register on the integrated circuit.

18. The method of claim 16 , further comprising writing the loop-gain adjustment to a register on the integrated circuit.