Multi-stage equalizer for inter-symbol interference cancellation
An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate. The ISI estimate from each stage is further equalized by application of the measures of low-frequency ISI from the first feed-forward stage and fed to the next in the cascade of stages. The ISI estimates from the stages thus become progressively more accurate. The number of stages applied to a given signal can be optimized to achieve a suitably low bit-error rate. Power is saved by disabling stages which are not required to meet that goal.
1. A receiver comprising:
a node to communicate a series of input symbols;
a first equalizer coupled to the node to produce first equalized symbols responsive to the series of input symbols;
a delay element coupled to the first equalizer to delay each of the first equalized symbols to produce delayed versions of the first equalized symbols;
a second equalizer coupled to the node to produce second equalized symbols responsive to the series of input symbols;
a decision circuit coupled to the second equalizer to issue a high-confidence decision for each of some of the second equalized symbols and a low-confidence decision for each of others of the second equalized symbols;
a third equalizer to equalize the high-confidence decisions and the low-confidence decisions; and
an arithmetic operator to combine the delayed versions of the first equalized symbols with the equalized high-confidence decisions and the equalized low-confidence decisions to produce third equalized symbols.
2. The receiver of claim 1 , further comprising an analog-to-digital converter to issue the series of input symbols responsive to an analog signal.
3. The receiver of claim 1 , further comprising a second decision circuit coupled to the arithmetic operator to issue a second high-confidence decision for each of the third equalized symbols.
4. The receiver of claim 3 , further comprising a third decision circuit coupled to the second equalizer to issue a third high-confidence decision for each of the second equalized symbols.
5. The receiver of claim 4 , further comprising a multiplexer coupled to the second decision circuit and the third decision circuit, the multiplexer to select between the second high-confidence decisions and the third high-confidence decisions.
6. The receiver of claim 5 , further comprising a power controller to disable the second equalizer when the multiplexer selects the third high-confidence decisions.
7. The receiver of claim 3 , wherein each of the second high-confidence decisions represents the third equalized symbols as a multi-bit digital value.
8. The receiver of claim 1 , wherein the first equalizer has a first number of filter taps, the second equalizer has a second number of filter taps, and the second number differs from the first number.
9. The receiver of claim 8 , wherein the second number is less than the first number.
10. The receiver of claim 8 , wherein the third equalizer has fewer taps than the first equalizer.
11. The receiver of claim 1 , wherein each of the high-confidence decisions represents one of N ranges of symbol amplitudes and each of the low-confidence decisions represents N−1 ranges of symbol amplitudes.
12. The receiver of claim 1 , further comprising:
a second delay element coupled to the first delay element to produce second delayed versions of the first equalized symbols;
a second decision circuit coupled to the arithmetic operator to issues a second high-confidence decision for some of the third equalized symbols and a second low-confidence decision for others of the third equalized symbols;
a fourth equalizer to equalize the second high-confidence decisions and the second low-confidence decisions; and
a second arithmetic operator to combine the second delayed versions of the first equalized symbols with the second equalized high-confidence decisions and the second equalized low-confidence decisions to produce fourth equalized symbols.
13. The receiver of claim 1 , wherein the first equalizer, the second equalizer, and the third equalizer are feed-forward equalizers.
14. A method of interpreting an input signal expressing a series of symbols, each of the symbols representing one of a set of possible symbol values, the method comprising:
equalizing the series of symbols to produce a first equalized series of symbols and a second equalized series of symbols;
delaying the first equalized series of symbols to produce a delayed equalized series of symbols;
sampling the second equalized series of symbols to obtain high-confidence symbol decisions and low-confidence symbol decisions;
equalizing the high-confidence symbol decisions and the low-confidence symbol decisions; and
combining the first delayed equalized series of symbols with the high-confidence symbol decisions and the low-confidence symbol decisions to produce a third equalized series of symbols.
15. The method of claim 14 , further comprising sampling the third equalized series of symbols.
16. The method of claim 14 , wherein equalizing the series of symbols to produce the first equalized series of symbols applies a first set of tap values and equalizing the series of symbols to produce the second equalized series of symbols applies a second set of tap values fewer than the first set of tap values.
17. The method of claim 16 , wherein the first set of tap values includes a main-tap value and the second set of tap values omits the main-tap value.
18. The method of claim 14 , further comprising:
delaying the delayed first equalized series of symbols to produce a second delayed equalized series of symbols;
sampling the third equalized series of symbols to obtain second high-confidence symbol decisions and second low-confidence symbol decisions;
equalizing the second high-confidence symbol decisions and the second low-confidence symbol decisions; and
combining the second delayed equalized series of symbols with the second high-confidence symbol decisions and the second low-confidence symbol decisions to produce a fourth equalized series of symbols.
19. The method of claim 18 , further comprising sampling the fourth equalized series of symbols.
20. The method of claim 19 , further comprising sampling the third equalized series of symbols and selecting between the sampled third equalized series of symbols and the sampled fourth equalized series of symbols.