Granted Patent B2

US 12,294,474 · App. 18/142,977 · Granted May 6, 2025

Inventor: Ehud Nir (Etobicoke, CA)

Assignee: Cadence Design Systems, Inc.

H04L25/03057H04L27/06H04L25/4917

Abstract

Claims (96)

1. A receiver comprising:

a sampling circuit configured to generate a plurality of samples of an incoming signal modulated according to a pulse-amplitude modulation (PAM) scheme; and

a digital processing circuit coupled to the sampling circuit, wherein the digital processing circuit comprises:

a partially unrolled decision feedback equalizer (DFE), wherein the partially unrolled DFE comprises a first multiplexers having two 1-bit inputs and one 1-bit output and a second multiplexer coupled to the first multiplexer, wherein the partially unrolled DFE is configured to determine a 1-bit output value; and

decompression circuitry configured to determine a PAM level region in which an actual symbol is located and transform the 1-bit output value into a multi-bit output value by adding a pointer value associated with the PAM level region within the PAM scheme.

2. The receiver of claim 1 , further comprising:

a first feed-forward equalizer (FFE), the first FFE configured to receive the plurality of samples and output a secondary FFE output value;

a multi-level slicer coupled to the first FFE, the multi-level slicer configured to output a partial decision based on the secondary FFE output value, wherein the partial decision comprises a partially equalized symbol and an error direction;

a decoder coupled to the multi-level slicer, the decoder configured to determine an indication of the PAM level region of the partially equalized symbol; and

a second FFE configured to receive the plurality of samples and output a primary FFE output value associated with a current sample, wherein the partially unrolled DFE is configured to output the 1-bit output value of the current sample using the partial decision and the primary FFE output value.

3. The receiver of claim 1 , wherein:

the PAM scheme comprises two or more levels; and

the partially unrolled DFE comprises one or more taps.

4. The receiver of claim 1 , wherein:

the PAM scheme comprises four levels; and

the partially unrolled DFE comprises one tap.

5. The receiver of claim 1 , wherein the partially unrolled DFE is a parallel DFE with a specified timing path to process P samples in parallel in a word clock domain, where P is a positive integer greater than two.

6. The receiver of claim 5 , wherein the parallel DFE, to meet the specified timing path, comprises a pre-calculation stage, a look-ahead stage, and an unrolling stage, wherein the look-ahead stage is to select a compressed look-ahead candidate of a current sample based on a partially equalized symbol of a previous sample, wherein the unrolling stage is to select a compressed sliced symbol of the current sample.

7. The receiver of claim 6 , wherein the pre-calculation stage is to calculate and slice a fully equalized signal based on speculations of N{circumflex over ( )}K possibilities, where N is a number of PAM levels in the PAM scheme, and K is a number of taps of the parallel DFE.

8. The receiver of claim 6 , further comprising a first feed-forward equalizer (FFE) configured to receive the plurality of samples and output the partially equalized symbol of the previous sample and an error direction, wherein an indication of the PAM level region in which an actual sliced symbol is located is determined based on the partially equalized symbol and the error direction.

9. The receiver of claim 8 , wherein a number of the first and second multiplexers is set forth in the following equation:

1

*

P

*

(

(

L

-

1

)

*

2

N

2

+

∑

i

=

0

N

-

1

2

i

)

where P represents a number of parallel lines, L represents a look-ahead factor, and N represents a number of taps of the partially unrolled DFE.

10. A method comprising:

receiving, by a processing device, a plurality of samples of an incoming signal modulated according to a pulse-amplitude modulation (PAM) scheme;

determining, by the processing device, a partial decision associated with a previous sample, wherein the partial decision comprises a partially equalized symbol and an error direction;

determining, by the processing device, an indication of a PAM level region of the partially equalized symbol;

determining, by the processing device, a number of compressed candidates using a threshold of the PAM level region;

generating, by the processing device, a DFE output based on an equalized signal corresponding to the incoming signal using the number of compressed candidates; and

transforming, by the processing device, the DFE output into a multi-bit output value by adding a pointer value associated with the PAM level region within the PAM scheme.

11. The method of claim 10 , further comprising:

determining, by a first feed-forward equalizer (FFE) of the processing device, a secondary FFE output value;

determining, by a multi-level slicer of the processing device, the partial decision based on the secondary FFE output value; and

determining, by a second FFE of the processing device, a primary FFE output value associated with a current sample, wherein:

generating the DFE output comprises determining, by a partially unrolled decision feedback equalizer (DFE) of the processing device, a compressed sliced decision of the current sample using the number of compressed candidates; and

transforming the DFE output into the multi-bit output value comprises adding the pointer value to the compressed sliced decision to obtain the multi-bit output value.

12. A system comprising:

an analog-to-digital converter (ADC) configured to receive an incoming signal and generate a plurality of samples according to a pulse-amplitude modulation (PAM) scheme; and

a digital signal processor (DSP) coupled to the ADC, wherein the DSP comprises a plurality of processing blocks comprising:

a first feed-forward equalizer (FFE) configured to output a first value associated with a previous sample of the plurality of samples;

a multi-level slicer configured to output a partially equalized symbol based on the first value and an error direction;

a decoder configured to determine an indication of a PAM level region in which an actual symbol is located based on the first value and the error direction;

a second FFE configured to output a second value associated with a current sample;

a decision feedback equalizer (DFE) comprising a plurality of multiplexers having two 1-bit inputs and one 1-bit output; and

decompression circuitry configured to transform a 1-bit output value into a multi-bit output value by adding a pointer value associated with the PAM level region within the PAM scheme, wherein the decoder comprises a multiplexer coupled to the multi-level slicer, and configured to output a first candidate and a second candidate based on the partially equalized symbol.

13. The system of claim 12 , wherein the plurality of multiplexers each having two 1-bit inputs and one 1-bit output, wherein a number of the plurality of multiplexers is set forth in the following equation:

1

*

P

*

(

(

L

-

1

)

*

2

N

2

+

∑

i

=

0

N

-

1

2

i

)

where P represents a number of parallel lines, L represents a look-ahead factor, and N represents a number of taps of the DFE.

Assignments (2)

Continuity (2)

References Cited (10)