IP Library Granted Patent US 12,057,975
Granted Patent B2
US 12,057,975 · App. 18/140,142 · Granted Aug 6, 2024

Live offset cancellation of the decision feedback equalization data slicers

Inventors: Mohammad Sadegh Jalali (Toronto, CA); Marcus Van Ierssel (Toronto, CA)
Assignee: Cadence Design Systems, Inc.
H04L25/03267H04L25/03057H04L25/03146
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Quick Facts
Patent No.
US 12,057,975
App. No.
18/140,142
Granted
Aug 6, 2024
Kind
B2
Abstract

A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.

Claims (29)

1. An integrated circuit, comprising:

comparator circuitry to receive an input signal, a first threshold, and a second threshold, and to, based on a first comparison of the input signal to the first threshold and a second comparison of the input signal to the second threshold, respectively produce a first comparison output and a second comparison output;

selection circuitry to, based on a previous selected value output by the selection circuitry, output a selected one of the first comparison output and a second comparison output as a selected value output by the selection circuitry and output an other one of the first comparison output and the second comparison output as a non-selected value output by the selection circuitry; and

adjustment circuitry to receive an adjustment value that is based on the non-selected value output by the selection circuitry, that alters an offset associated with a one of the first comparison and the second comparison.

2. The integrated circuit of claim 1 , wherein the adjustment value is further based on a plurality of non-selected values output by the selection circuitry.

3. The integrated circuit of claim 2 , wherein the adjustment value is based on a statistical property of the plurality of non-selected values output by the selection circuitry.

4. The integrated circuit of claim 3 , wherein the statistical property is based on a first count of a first value in the non-selected values output by the selection circuitry and a second count of a second value in the non-selected values output by the selection circuitry.

5. The integrated circuit of claim 3 , wherein the adjustment value is based on equalizing a first count of a first value in the non-selected values output by the selection circuitry and a second count of a second value in the non-selected values output by the selection circuitry.

6. The integrated circuit of claim 3 , wherein the adjustment value is based on equalizing a first percentage associated with a first value in the non-selected values output by the selection circuitry and a second percentage associated with a second value in the non-selected values output by the selection circuitry.

7. The integrated circuit of claim 1 , wherein the adjustment value is received from a separate integrated circuit.

8. A system, comprising:

circuitry configured to receive a first plurality of output values produced by first comparisons between an input signal and a first threshold, and to receive a second plurality of output values produced, concurrently with the first comparisons, by second comparisons between the input signal and a second threshold;

circuitry configured to select between concurrently produced ones of the first plurality of output values and ones of the second plurality of output values to produce a plurality of selected output values and a plurality of non-selected output values, the selection between concurrently produced ones of the first plurality of output values and ones of the second plurality of output values to be based on a previous one of the plurality of selected output values; and

circuitry configured to, based on the plurality of non-selected output values, adjust a first input offset of third comparisons between the input signal and the first threshold.

9. The system of claim 8 , wherein a second input offset of fourth comparisons between the input signal and the second threshold is based on the plurality of non-selected output values.

10. The system of claim 9 , wherein the first input offset is adjusted based on a first statistical property of the plurality of non-selected output values and the second input offset is adjusted based on a second statistical property of the plurality of non-selected output values.

11. The system of claim 10 , wherein the first statistical property is based on a first count of a first value in the non-selected output values and a second count of a second value in the non-selected output values and the second statistical property is based on a third count of a first value in the non-selected output values and a fourth count of a second value in the non-selected output values.

12. The system of claim 8 , wherein the first input offset is adjusted based on a first statistical property of the plurality of non-selected output values.

13. The system of claim 12 , wherein the first statistical property is based on a first count of a first value in the non-selected output values and a second count of a second value in the non-selected output values.

14. The system of claim 12 , wherein the first input offset is adjusted based on equalizing a first count of a first value in the non-selected output values and a second count of a second value in the non-selected output values.

15. The system of claim 12 , wherein the first input offset is based on equalizing a first percentage associated with a first value in the non-selected output values and a second percentage associated with a second value in the non-selected output values.

16. A method of adjusting an input offset voltage of a comparator, comprising: receiving a first plurality of output values corresponding to a corresponding first plurality of comparisons of an input signal to a first threshold;

receiving a second plurality of output values corresponding to a corresponding second plurality of comparisons of the input signal to a second threshold;

selecting, based on at least one previously selected output value, between each one of the first plurality of output values and each one of the second plurality of output values that were concurrently produced to produce a plurality of selected output values and a plurality of non-selected output values; and

based on the plurality of non-selected output values, adjusting the input offset voltage of the comparator.

17. The method of claim 16 , wherein the comparator produced the first plurality of output values.

18. The method of claim 16 , wherein the comparator produced the second plurality of output values.

19. The method of claim 16 , further comprising: performing a statistical analysis of the plurality of non-selected output values.

20. The method of claim 16 , wherein the first plurality of output values are a result of a non-contiguous set of comparisons by the comparator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2023
From: RAMBUS INC.
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 065017/0449 →
Continuity (3)
Continuation 17298165
Provisional Application 62778734 · Dec 12, 2018
Related Publication 20230388163A1 · Nov 30, 2023