Low jitter clock multiplier circuit and method with arbitrary frequency acquisition
A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.
1. A clock generation circuit for generating a clock signal at a desired frequency based on a high-frequency clock signal, the high-frequency clock signal having a frequency equal to the desired frequency multiplied by a frequency multiple, comprising:
a clock divider configured to apply a divide ratio to the high-frequency clock signal to generate a divided clock signal, the divide ratio being equal to the frequency multiple rounded up or down to an integer value;
a variable skew control block configured to:
apply a delay to the divided clock signal to generate a first portion of a feedback clock signal such that an edge of the first portion of the feedback clock is delayed to coincide with a corresponding edge of the high-frequency clock signal divided by the frequency multiple; and
repeat one or more times a step of applying an additional delay to the divided clock signal to generate one or more additional portions of the feedback clock signal such that an edge of each additional portion of the feedback clock is delayed to coincide with a corresponding edge of the high-frequency clock signal divided by the frequency multiple.
2. The clock generation circuit of claim 1 , wherein the clock divider applies the divide ratio in response to receiving a clock divider control signal.
3. The clock generation circuit of claim 2 , wherein the variable skew control block applies the delay and each additional delay in response to receiving variable skew control signals.
4. The clock generation circuit of claim 3 , further comprising:
a phase-locked-loop digital-to-time converter configured to compare the feedback clock signal to a reference clock signal; and
a clock control unit configured to generate the clock divider control signal and variable skew control signals based on the comparison of the feedback clock signal to the reference clock signal.
5. The clock generation circuit of claim 4 , wherein:
the phase-locked-loop digital-to-time converter compares the feedback clock signal to the reference clock signal by measuring a relative phase difference between the feedback clock signal and the reference clock signal; and
the clock control unit is configured to receive the measured relative phase difference from the phase-locked-loop digital-to-time converter.
6. The clock generation circuit of claim 5 , further comprising a clock generator block configured to generate the high-frequency clock signal based on the relative phase difference between the feedback clock signal and the reference clock signal.
7. A method for generating a clock signal at a desired frequency, comprising:
receiving a high-frequency clock signal, the high-frequency clock signal having a frequency equal to the desired frequency multiplied by a frequency multiple;
using a clock divider to apply a divide ratio to the high-frequency clock signal to generate a divided clock signal, the divide ratio being equal to the frequency multiple rounded up or down to an integer value;
using a variable skew control block to apply a delay to the divided clock signal to generate a first portion of a feedback clock signal such that an edge of the first portion of the feedback clock is delayed to coincide with a corresponding edge of the high-frequency clock signal divided by the frequency multiple; and
repeating one or more times a step of applying an additional delay to the divided clock signal to generate one or more additional portions of the feedback clock signal such that an edge of each additional portion of the feedback clock is delayed to coincide with a corresponding edge of the high-frequency clock signal divided by the frequency multiple.
8. The method of claim 7 , wherein the clock divider applies the divide ratio in response to receiving a clock divider control signal.
9. The method of claim 8 , wherein the variable skew control block applies the delay and each additional delay in response to receiving variable skew control signals.
10. The method of claim 9 , further comprising generating the clock divider control signal and variable skew control signals based on a comparison of the feedback clock signal to a reference clock signal.
11. The method of claim 10 , wherein the comparison of the feedback clock signal to the reference clock signal comprises measuring a relative phase difference between the feedback clock signal and the reference clock signal.
12. The method of claim 11 , further comprising generating the high-frequency clock signal based on the relative phase difference between the feedback clock signal and the reference clock signal.