Granted Patent B1

US 12,603,655 · App. 18/624,299 · Granted Apr 14, 2026

Inventors: Sudipta Sarkar (San Jose, CA); Angus McLaren (Dundas, CA); Meenakshi S. (Bengaluru, IN); Priya T K (Bangalore, IN); Srivatsa Ranganatha (Bangalore, IN); Mohammed Ranjbar (San Jose, CA); Paul Lee (San Francisco, CA); Shwetabh Verma (Los Altos, CA); George Chung Fai Ng (Markham, CA)

Assignee: Cadence Design Systems, Inc.

H03L7/0992H03L7/0891H03L7/091H03L2207/50

Abstract

Claims (29)

1 . A subranging digital to time converter-based fractional phase locked loop circuit comprising:

a digital to time converter including a coarse digital to time converter and a fine digital to time converter, wherein the coarse digital to time converter utilizes pseudo-random signal based randomization and the digital to time converter requires no integral non-linearity calibration;

a phase detector circuit configured to receive a reference frequency and an output of the digital to time converter;

a phase frequency detector/charge pump circuit configured to receive the reference frequency and the output of the digital to time converter;

a loop filter and voltage-controlled oscillator (VCO) circuit configured to receive an output of the phase frequency detector/charge pump circuit, wherein the pseudo-random signal based randomization is configured to selectively add a fraction of a VCO period to a first delay associated with the coarse digital to time converter, and to simultaneously subtract the same fraction of the VCO period from a second delay associated with the fine digital to time converter; and

a divider circuit configured to receive an output of the voltage-controlled oscillator circuit and to transmit a signal to the digital to time converter.

2 . The circuit of claim 1 , wherein the phase detector circuit includes a Bang-Bang phase detector.

3 . The circuit of claim 1 , wherein the fine digital to time converter receives an input from the course digital to time converter to generate a sub-ranging digital to time converter.

4 . The circuit of claim 1 , wherein the fine digital to time converter calibrates a fine digital to time converter gain error.

5 . The circuit claim 1 , further comprising a complementary fine digital to time converter.

6 . The circuit of claim 1 , further comprising a delta sigma modulator circuit configured to produce a number and to transmit the number to the divider circuitry.

7 . The circuit of claim 1 , wherein the fine digital to time converter does not include a non-linear calibration.

8 . The circuit claim 1 , wherein the coarse digital to time converter does not include a calibration.

9 . A subranging digital to time converter-based fractional phase locked loop method comprising:

providing a digital to time converter including a coarse digital to time converter and a fine digital to time converter, wherein the coarse digital to time converter utilizes pseudo-random signal based randomization and the digital to time converter requires no integral non-linearity calibration;

receiving a reference frequency and an output of the digital to time converter at a phase detector circuit;

receiving the reference frequency and the output of the digital to time converter at a phase frequency detector/charge pump circuit;

receiving an output of the phase frequency detector/charge pump circuit at a loop filter and voltage-controlled oscillator (VCO) circuit, wherein the pseudo-random signal based randomization is configured to selectively add a fraction of a VCO period to a first delay associated with the coarse digital to time converter, and to simultaneously subtract the same fraction of the VCO period from a second delay associated with the fine digital to time converter;

receiving an output of the voltage-controlled oscillator circuit at a divider circuit; and

transmitting a signal from the divider circuit to the digital to time converter.

10 . The method of claim 9 , wherein the phase detector circuit includes a Bang-Bang phase detector.

11 . The method of claim 9 , further comprising:

receiving an input from the course digital to time converter at the fine digital to time converter to generate a sub-ranging digital to time converter.

12 . The method of claim 9 , further comprising:

calibrating a fine digital to time converter gain error at the fine digital to time converter.

13 . The method of claim 9 , further comprising a complementary fine digital to time converter.

14 . The method of claim 9 , further comprising a delta sigma modulator circuit configured to produce a number and to transmit the number to the divider circuitry.

15 . The method of claim 9 , wherein the fine digital to time converter does not include a non-linear calibration.

16 . The method of claim 9 , wherein the coarse digital to time converter does not include a calibration.

Assignments (1)

References Cited (172)