Synchronization of a data output signal to a clock input
View Patent ↗A method for synchronizing an output signal of a device phase aligned with an input clock includes the steps of providing an oscillator signal having a period Πn of 1/(f 1 *2 n ), wherein f 1 is the clock frequency, and wherein the oscillator signal is phase aligned with the input clock signal, so a multiple of the clock frequency is produced. A number of delayed signals are generated, each having the same period as the input clock signal, but delayed by multiples of one-half the oscillator period from the input clock. The phase difference between the unadjusted output signal each delayed signal is determined, and the smallest value of the phase difference calculated. This smallest phase difference value is then added to the clock signal, resulting in a delayed clock, which is then used to generated the delayed output signal, which will be in close synchronization with the input clock.
1. A method for synchronizing an output signal of a device so as to be phase aligned with an input clock signal comprises the steps of:
a) providing an oscillator signal having a period Πn of 1/(f 1 *2 n ), wherein n is an integer, wherein f 1 is the clock frequency, and wherein the oscillator signal is phase aligned with the input clock signal;
b) generating a multiplicity of delayed signals sdk, where k is an integer, each delayed signal having the same period Πc as the input clock signal, wherein delayed signal sd 1 is delayed by one-half the oscillator period Πn from the input clock signal, and wherein delayed signal sd(k+1) is delayed by one-half the oscillator period Πn from delayed signal sdk for each value of k;
c) measuring the phase difference ΔΦk between an unadjusted output signal and the delayed signal sdk for each value of k;
d) determining which value of k, equal to km, resulted in the smallest positive value of ΔΦk measured;
e) adding a coarse delay time Δτ 1 to the clock signal equivalent to the smallest positive value of ΔΦk measured, creating a delayed clock signal thereby;
f) generating a new output signal, delayed by time Δτ 1 from the output signal, by use of the delayed clock signal.
2. The method of claim 1 , wherein the phase alignment of the oscillator signal with the input clock signal is effected by aligning a rising edge of the oscillator signal with a rising edge of the input clock signal.
3. The method of claim 1 , wherein generating the output signal further comprises gating it.
4. The method of claim 1 , further comprising generating a fine delay time by the steps of:
(a) determining the phase difference ΔΦk 2 between the new output signal and the delayed signal sdk corresponding to k=km;
(b) calculating fine time delay Δτ 2 , equivalent to the phase difference ΔΦk 2 ; and
(c) adding a delay of Δτ 2 to the delayed clock signal.
5. The method of claim 3 , wherein generating of the fine delay time further comprises passing the output signal through a delay tree.
6. The method of claim 5 , wherein generating the fine delay time further comprises selecting the branches of the delay tree which produces the delay closest in magnitude to Δτ 2 .
7. The method of claim 6 , wherein the delay tree further comprises a multiplicity of gates of preselected delay characteristics with a multiplicity of selection taps.