Fin FET and method of fabricating same
View Patent ↗A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.
1. A structure of a fin field effect transistor (fin FET) formed on a bulk silicon substrate on which an active region and a non-active region are defined by a device isolation film, said structure comprising:
a fin active region having a protrusion shape with a step coverage of predetermined height from the device isolation film;
a first recess having a first depth measured from an upper surface of the fin active region in the device isolation film;
a gate electrode that is in a second recess having a second depth from an upper surface of the fin active region and extends beyond the upper surface of the fin active region, the second depth less than the first depth;
a gate insulation layer disposed between the fin active region and the gate electrode, the gate insulation layer within the second recess; and
a source/drain region disposed in the fin active region on both sides of the gate electrode.
2. The structure of claim 1 , wherein the upper surface of the fin active region is about 1000 Å to 1500 Å taller than an upper surface of the device isolation film.
3. The structure of claim 1 , wherein an upper edge portion of the fin active region is rounded.
4. The structure of claim 1 , wherein the gate electrode has a depth of about 300 Å to 350 Å from the upper surface of the fin active region.
5. The structure of claim 1 , wherein a bottom face of the gate electrode is rounded and has a predetermined depth from the upper surface of the fin active region.
6. The structure of claim 1 , further comprising a threshold voltage control region disposed beneath the gate insulation layer.
7. The structure of claim 1 , wherein the gate electrode has a dual gate structure.
8. The structure of claim 1 , wherein a bottom face of the gate electrode extends to the second depth within the fin active region from the upper surface of the fin active region.
9. The structure of claim 1 , wherein the rounded bottom face of the gate electrode extends into the fin active region from the upper surface of the fin active region.
10. The structure of claim 1 , wherein the upper surface of the fin active region is taller than an upper surface of the device isolation film.
11. The structure of claim 1 , wherein the gate electrode extends beyond the upper surface of the fin active region into the fin active region.
12. The structure of claim 1 , wherein the gate electrode comprises a first gate electrode, the structure further comprising a second gate electrode that is in the first recess.