IP Library Granted Patent US 7,321,285
Granted Patent B2
US 7,321,285 · App. 11/736,565 · Granted Jan 22, 2008

Method for fabricating a transformer integrated with a semiconductor structure

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Quick Facts
Patent No.
US 7,321,285
App. No.
11/736,565
Granted
Jan 22, 2008
Kind
B2
Abstract

A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.

Claims (18)

1. A transformer integrated with a semiconductor structure comprising:

a substrate;

a primary winding layer and a top interconnection metal layer formed on the substrate;

a passivation layer formed on the primary winding layer and the top interconnection metal layer, and the passivation layer having a plurality of openings exposing parts of the top interconnection metal layer; and

a secondary winding layer and at least a bonding pad respectively formed on the passivation layer and the top interconnection metal layer, and the bonding pad being electrically connected to the top interconnection metal layer through the openings;

wherein the primary winding layer and the secondary winding layer construct the transformer.

2. The transformer of claim 1 , wherein the substrate comprises an active circuit and at least an interconnection metal layer.

3. The transformer of claim 1 , wherein the passivation has a thickness in a range of 100-500 angstroms.

4. The transformer of claim 1 , wherein the primary winding layer comprises copper.

5. The transformer of claim 1 , wherein the secondary winding layer comprises titanium, titanium oxide, aluminum, or alloys of the aforementioned metals.

6. The transformer of claim 1 , wherein the primary winding layer and the secondary winding layer respectively comprise a coil pattern.

7. The transformer of claim 6 , wherein the coil patterns of the primary winding layer and the secondary winding layer are partially overlapping.

8. The transformer of claim 7 , wherein the coil patterns of the primary winding layer and the secondary winding layer are preferably coaxial.

9. The transformer of claim 6 , wherein the width of the primary coil layer is smaller than the width of the secondary coil layer.

10. The transformer of claim 1 , wherein the primary winding layer and the top interconnection metal layer are approximately integrated in the same horizontal level.

11. The transformer of claim 1 , wherein the secondary winding layer and the bonding pad are approximately integrated in the same horizontal level.

12. The transformer of claim 1 further comprising a protection layer on the substrate, the protection layer covering the secondary winding layer and exposing the bonding pad.

13. The transformer of claim 12 , wherein the protection comprises silicon nitride.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2007
From: HUNG, CHENG-CHOU; TSENG, HUA-CHOU; LIANG, VICTOR-CHIANG; CHEN, YU-CHIA; HSU, TSUN-LAI
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 019174/0705 →