FIELD EFFECT TRANSISTOR WITH INVERTED T SHAPED GATE ELECTRODE AND METHODS FOR FABRICATION THEREOF
A semiconductor structure includes an inverted T shaped gate electrode located over a channel region that separates a plurality of source and drain regions within a semiconductor substrate. The inverted T shaped gate electrode may comprise different gate electrode materials in a horizontal portion thereof and a vertical portion thereof. The semiconductor structure may be passivated with an inter-level dielectric (ILD) layer through which may be located and formed a plurality of vias that contact the plurality of source and drain regions. Due to the inverted T shaped gate electrode, the semiconductor structure exhibits a reduced gate electrode to via capacitance.
1 . A semiconductor structure comprising a gate electrode located over a channel region that separates a plurality of source and drain regions within a semiconductor substrate, wherein the gate electrode has an inverted T shape.
2 . The semiconductor structure of claim 1 wherein the semiconductor structure comprises a planar field effect transistor.
3 . The semiconductor structure of claim 1 wherein:
a horizontal portion of the inverted T shape comprises a first gate electrode material; and
a vertical portion of the inverted T shape comprises a second gate electrode material different than the first gate electrode material.
4 . The semiconductor structure of claim 3 wherein:
the first gate electrode material comprises a metal material; and
the second gate electrode material comprises a polysilicon material.
5 . The semiconductor structure of claim 3 wherein:
the first gate electrode material comprises a metal material laminated upon a polysilicon material; and
the second gate electrode material comprises a polysilicon material.
6 . A method for fabricating a semiconductor structure comprising:
providing a second gate electrode material layer aligned with a first gate electrode material layer different from the second gate electrode material layer over a semiconductor substrate;
thinning the second gate electrode material layer with respect to the first gate electrode material layer to provide an inverted T shaped gate electrode from a thinned second gate electrode material layer and the first gate electrode material layer; and
forming into the semiconductor substrate while using the inverted T shaped gate electrode as a mask a plurality of source and drain regions.
7 . The method of claim 6 wherein the providing includes:
using the first gate electrode material layer that comprises a metal material; and
using the second gate electrode material layer that comprises a polysilicon material.
8 . The method of claim 6 wherein the providing includes:
using the first gate electrode material layer that comprises a metal material laminated upon a polysilicon material; and
using the second gate electrode material layer that comprises a polysilicon material.
9 . The method of claim 6 wherein the thinning uses an isotropic etch method that thins the second gate electrode material layer by lateral undercutting beneath a capping layer that is formed aligned upon the second gate electrode material layer.
10 . The method of claim 9 wherein each side of the lateral undercutting beneath the capping layer is about one-third a linewidth of the capping layer.
11 . The method of claim 6 further comprising forming an inter-level dielectric (ILD) layer covering the inverted T shaped gate electrode and the plurality of source and drain regions.
12 . The method of claim 11 further comprising forming a plurality of vias through the inter-level dielectric (ILD) layer and contacting the plurality of source and drain regions.
13 . The method of claim 12 wherein the inverted T shaped gate electrode provides a reduced gate electrode to via capacitance within the semiconductor structure.
14 . A method for fabricating a semiconductor structure comprising:
providing a patterned second gate electrode material layer upon a first gate electrode material layer different from the patterned second gate electrode material layer over a semiconductor substrate;
forming a spacer adjoining the patterned second gate electrode material layer;
etching the first gate electrode material layer while using the patterned second gate electrode material layer and the spacer as a mask to provide an inverted T shaped gate electrode from the patterned second gate electrode material layer and a patterned first gate electrode material layer patterned from the first gate electrode material layer; and
forming into the semiconductor substrate while using at least the inverted T shaped gate electrode as a mask a plurality of source and drain regions.
15 . The method of claim 14 wherein the providing includes:
using the first gate electrode material layer that comprises a metal material; and
using the second gate electrode material layer that comprises a polysilicon material.
16 . The method of claim 14 wherein the providing includes:
using the first gate electrode material layer that comprises a metal material laminated upon a polysilicon material; and
using the second gate electrode material layer that comprises a polysilicon material.
17 . The method of claim 14 wherein the forming the spacer uses an anisotropic etch method.
18 . The method of claim 14 further comprising forming an inter-level dielectric (ILD) layer covering the inverted T shaped gate electrode and the plurality of source and drain regions.
19 . The method of claim 18 further comprising forming a plurality of vias through the inter-level dielectric (ILD) layer and contacting the plurality of source and drain regions.
20 . The method of claim 19 wherein the inverted T shaped gate electrode provides a reduced gate electrode to via capacitance within the semiconductor structure.