Efficient hardware implementation of tweakable block cipher
View Patent ↗A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T (n+1) basing on known T n. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).
1. A method of computing whitening vectors, the method comprising:
(A) entering a tweakable 128-bit key T to a first functional unit to produce a 128-bit T 0 value, where
T 0 =TØ3,
(B) entering To into a second functional unit to produce 128 128-bit values T 1 -T 128 , where,
T 1 =T 0 2,
T 2 =T 1 2,
T 128 =T 127 2,
(C) entering a 128-bit address value n into a third functional unit to produce 7-bit m values, where m represents a count of trailing values of one in a binary expansion of the address value n,
(D) using the address value n, reduce the values T 1-128 in a fourth functional unit to produce one 128-bit value T m+1 , by:
(i) using the least significant bit m 0 of m, compute sixty-four 128-bit values, by:
T 1.0 =m 0 ?T 1 :T 2 ,
T 2.0 =m 0 ?T 3 :T 4 ,
T 3.0 =m 0 ?T 5 :T 6 ,
T 64.0 =m 0 ?T 127 :T 128 ,
(ii) using the second least significant bit m 1 of m, compute thirty-two 128-bit values, by:
T 1.1 =m 1 ?T 1.0 :T 2.0,
T 2.1 =m 1 ?T 3.0 :T 4.0,
T 3.1 =m 1 ?T 5.0 :T 6.0,
T 32.1 =m 1 ?T 63.0 :T 64.0,
(iii) using the third least significant bit m 2 of m, compute sixteen 128-bit values, by:
T 1.2 =m 2 ?T 1.1 :T 2.1,
T 2.2 =m 2 ?T 3.1 :T 4.1,
T 3.2 =m 2 ?T 5.1 :T 6.1,
T 16.2 =m 2 ?T 31.1 :T 32.1,
(iv) using the fourth least significant bit m 3 of m, compute eight 128-bit values in the same manner as described in steps (D)(i) through (D)(iii),
(v) using the fifth least significant bit m 4 of m, compute four 128-bit values in the same manner as described in steps (D)(i) through (D)(iii),
(vi) using the sixth least significant bit m 5 of m, compute two 128-bit values in the same manner as described in steps (D)(i) through (D)(iii), and
(vii) using the seventh least significant bit m 6 of m, compute the 128-bit value T m+1 in the same manner as described in steps (D)(i) through (D)(iii),
(E) input T m+1 and T 0 into a fifth functional unit to compute differential D T (n)=T m+1 ⊕T 0 , and
(F) using the differential D T (n), compute whitening vector P n+1 =P n ⊕D T (n+1) and use P n+1 to encrypt/decrypt a data block for storage, where P n0 has been computed in an external multiplication unit once, at a beginning of a series of sequentially indexed data blocks.
2. The method of claim 1 , further comprising:
computing the whitening vector for each n,
XORing the whitening vector with an input block of data,
sending the XORed input block of data through an AES unit to produce an output block of data, and
XORing the output block of data with the whitening vector.
3. The method of claim 1 , further comprising:
computing the differentials using separate first and second processes that function identically and with a time shift between the two processes that is equal to a latency of the AES unit,
where when the first process produces the whitening vector P t at moment t, the AES unit finishes processing the t-th data block at t+latency(AES), and the second process has the whitening vector P t ready at t+latency(AES).
4. The method of claim 1 , wherein calculations are performed only for values of n that are divisible by two, as:
D 1( n )= T,
D 2( n )= D T ( n/ 2) 2= D T 2 ( n/ 2),
P n+1 =P n ⊕D 1( n ), and
P n+2 =P n ⊕D 2( n )
5. The method of claim 4 , further comprising:
computing the whitening vector for each n,
XORing the whitening vector with an input block of data,
sending the XORed input block of data through an AES unit to produce an output block of data, and
XORing the output block of data with the whitening vector.
6. The method of claim 5 , further comprising:
computing the differentials using separate first and second processes that function identically and with a time shift between the two processes that is equal to a latency of the AES unit,
where when the first process produces the whitening vector P t at moment t, the AES unit finishes processing the t-th data block at t+latency(AES), and the second process has the whitening vector P t ready at t+latency(AES).
7. The method of claim 1 , wherein calculations are performed only for values of n that are divisible by four, as:
D 1( n )= D 1( n+ 2)= T,
D 1′( n+ 1)= T 3,
D 4( n )= D T ( n/ 4) 4= D T 4 ( n/ 4),
P +1 =P n ⊕D 1( n ),
P n+2 =P n+1 ⊕D 1′( n+ 1),
P n+3 =P n+2 ⊕D 1( n+ 2), and
P n+4 =P n ⊕D 4( n )
8. The method of claim 7 , further comprising:
computing the whitening vector for each n,
XORing the whitening vector with an input block of data,
sending the XORed input block of data through an AES unit to produce an output block of data, and
XORing the output block of data with the whitening vector.
9. The method of claim 8 , further comprising:
computing the differentials using separate first and second processes that function identically and with a time shift between the two processes that is equal to a latency of the AES unit,
where when the first process produces the whitening vector P t at moment t, the AES unit finishes processing the t-th data block at t+latency(AES), and the second process has the whitening vector P t ready at t+latency(AES).
10. The method of claim 1 , wherein calculations are performed only for values of n that are divisible by K=2 k , where k>0, as:
for 0<i<K, P n+i =P n+i−1 ⊕+D1(n+i−1), and
P n+K =P n ⊕DK(n), where DK(n)=D T (n/K) K=D T K (n/K).
11. The method of claim 10 , further comprising:
computing the whitening vector for each n,
XORing the whitening vector with an input block of data,
sending the XORed input block of data through an AES unit to produce an output block of data, and
XORing the output block of data with the whitening vector.
12. The method of claim 11 , further comprising:
computing the differentials using separate first and second processes that function identically and with a time shift between the two processes that is equal to a latency of the AES unit,
where when the first process produces the whitening vector P t at moment t, the AES unit finishes processing the t-th data block at t+latency(AES), and the second process has the whitening vector P t ready at t+latency(AES).
13. The method of claim 1 , wherein calculations are performed only for values of n that are divisible by K=2 k , where k>0, as:
for 0<i<K, P n+i =P n+i−1 ⊕D 1 (n+i−1), and
P n+K =T{circle around (×)}(n+K).
14. The method of claim 13 , further comprising:
computing the whitening vector for each n,
XORing the whitening vector with an input block of data,
sending the XORed input block of data through an AES unit to produce an output block of data, and
XORing the output block of data with the whitening vector.
15. The method of claim 14 , further comprising:
computing the differentials using separate first and second processes that function identically and with a time shift between the two processes that is equal to a latency of the AES unit,
where when the first process produces the whitening vector P t at moment t, the AES unit finishes processing the t-th data block at t+latency(AES), and the second process has the whitening vector P t ready at t+latency(AES).