IP Library Granted Patent US 7,353,599
Granted Patent B2
US 7,353,599 · App. 11/742,858 · Granted Apr 8, 2008

Fiducial markings for quality verification of high density circuit board connectors

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Quick Facts
Patent No.
US 7,353,599
App. No.
11/742,858
Granted
Apr 8, 2008
Kind
B2
Abstract

Methods for qualifying the accuracy of a circuit board may include providing a printing mask pattern for first and second sides of the circuit board with a first sequence of spaced indicia parallel to a first edge of the printed circuit board, and a second sequence of spaced indicia parallel to a second edge of the printed circuit board opposite the first edge. A layer of visually conspicuous material may be printed on the board using the mask patterns. The board may be separated or cut to a predetermined size thereby removing, at least a portion of the spaced indicia of each sequence. The number of indicia printed on the first and second sides respectively of the circuit board may be determined after the circuit board is cut to the predetermined size. The circuit board may be accepted or rejected based upon the numerical determination against a qualification criteria.

Claims (27)

1. A method of qualifying the accuracy of a printed circuit board comprising:

providing a printing mask pattern for a first side of the printed circuit board with a first sequence of spaced indicia parallel to a first edge of the printed circuit board, and a second sequence of spaced indicia parallel to a second edge of the printed circuit board opposite said first edge;

printing a layer of visually conspicuous material on said first side of the printed circuit board using said printing mask pattern;

separating or cutting the printed circuit board to a predetermined size thereby removing, at least a portion of some of said spaced indicia of each sequence;

determining the number of indicia printed along said first edge and said second edge of the printed circuit board, after the printed circuit board is cut to said predetermined size; and

based upon such numerical determination against a qualification criteria accepting or rejecting the printed circuit board.

2. The method as defined in claim 1 , wherein the method of separating includes routing.

3. The method according to claim 1 , comprising determining a separation or cutting boundary for said separating or cutting of the printed circuit board based on said printing mask.

4. The method according to claim 1 , wherein at least a portion of said spaced indicia for said printing mask are arrayed in a staggered sequence of steps diverging away from an edge of the printed circuit board disposed between said first edge and said second edge.

5. A method of qualifying the accuracy of a printed circuit board comprising:

providing a printing mask pattern for a first side of the printed circuit board with a first sequence of spaced indicia parallel to a first edge of the printed circuit board, and a second sequence of spaced indicia parallel to a second edge of the printed circuit board opposite said first edge;

providing a printing mask pattern for a second side of the printed circuit board with a first sequence of spaced indicia parallel to said first edge of the printed circuit board, and a second sequence of spaced indicia parallel to a second edge of the board opposite said first edge;

printing a layer of visually conspicuous material on the printed circuit board using said mask patterns;

separating or cutting the printed circuit board to a predetermined size thereby removing, at least a portion of some of said spaced indicia of each sequence;

determining the number of indicia printed on said first and second sides respectively of the printed circuit board after the printed circuit board is cut to said predetermined size; and

based upon such numerical determination against a qualification criteria, accepting or rejecting the printed circuit board.

6. The method according to claim 5 , comprising determining an optimal size for the printed circuit board, based on said determined number.

7. The method according to claim 6 , wherein said optimal size comprises an optimal width of the printed circuit board, said optimal width corresponding to said determined number.

8. The method according to claim 5 , wherein said first sequence of said plurality of spaced indicia and said second sequence of said plurality of spaced indicia for one or both of said first printing mask and said second printing mask comprise staggered indicia.

9. The method according to claim 5 , wherein at least a portion of said spaced indicia for said first printing mask and said second printing mask are arrayed in a staggered sequence of steps diverging away from an edge of the printed circuit board disposed between said first edge and said second edge.

10. The method as defined in claim 5 , wherein a plurality of printed circuit boards are implemented on a panel, and further comprising separating the printed circuit board from the panel prior to said determining step.

11. The method as defined in claim 5 , wherein the method of separating includes routing.

12. The method according to claim 5 , comprising determining a separation or cutting boundary for said separating or cutting of the printed circuit board based on said first printing mask and said second printing mask.

13. The method according to claim 5 , wherein said qualification criteria is stored in a look-up table.

14. The method according to claim 5 , wherein said determining step is performed via a human visual inspection or an automated computer inspection.

15. The method according to claim 5 , wherein said determining step comprises determining the number of indicia appearing on said first edge and said second edge of the printed circuit board.

16. The method according to claim 5 , wherein said layer of visually conspicuous material and a plurality of pin contacts are placed on the printed circuit board using a single printing step.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2013
From: EMCORE CORPORATION
To: SUMITOMO ELECTRIC DEVICE INNOVATIONS, U.S.A., INC.
Reel/Frame 030006/0126 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2013
From: LAU, EDWARD WARMING; WANG, XIAOZHONG; MOSEBAR, ROBERT LEWIS
To: EMCORE CORPORATION
Reel/Frame 029693/0229 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded May 11, 2012
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: EMCORE CORPORATION; EMCORE SOLAR POWER, INC.
Reel/Frame 028192/0189 →
SECURITY AGREEMENT Recorded May 18, 2011
From: EMCORE CORPORATION; EMCORE SOLAR POWER, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 026304/0142 →