Memory cell for content-addressable memory
A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.
1. A memory cell for use in a content-addressable memory, the memory cell comprising:
a first latch, the first latch operative to store a first bit associated with a first stored word;
a second latch, the second latch operative to store a second bit associated with a second stored word;
a first logic gate, the first logic gate coupled to the first latch; and
a second logic gate, the second logic gate coupled to the second latch;
wherein the first and second latches collectively comprise a plurality of latch transistors, each of the plurality of latch transistors comprising a respective channel, the channels being oriented in substantially the same direction; and
wherein the memory cell comprises a central portion in which the first and second latches are implemented, and first and second side portions arranged on opposite sides of the central portion, the first and second logic gates being implemented in the side portions.
2. The memory cell of claim 1 , wherein at least one of the first and second latches comprises a static random access memory latch.
3. The memory cell of claim 1 , wherein at least one of the first and second latches comprises four n-type metal-oxide-semiconductor field effect transistors (MOSFETs) and two p-type MOSFETs.
4. The memory cell of claim 1 , wherein the plurality of latch transistors is switched using eight discrete gate lines.
5. The memory cell of claim 1 , wherein at least one of the first and second logic gates comprises four transistors.
6. The memory cell of claim 1 , wherein at least one of the first and second logic gates comprises an exclusive-or logic gate.
7. The memory cell of claim 1 , wherein the first and second logic gates collectively comprise a plurality of logic gate transistors, each of the plurality of logic gate transistors comprising a respective channel, the channels of the logic gate transistors being oriented in substantially the same direction as the channels of the plurality of latch transistors.
8. The memory cell of the claim 7 , wherein the plurality of logic gate transistors is switched using eight discrete gate lines.
9. The memory cell of claim 1 , wherein the memory cell occupies an area defined by two commonly oriented and partially abutting rectangular regions.
10. The memory cell of claim 1 , wherein the memory cell includes a metallization level comprising:
a first match line;
a first word line, the first word line substantially parallel with and adjacent to the first match line;
a second match line, the second match line substantially parallel with and adjacent to the first word line; and
a second word line, the second word line substantially parallel with and adjacent to the second match line.
11. A method of forming a memory cell for use in a content-addressable memory, the method comprising the steps of:
forming a first latch, the first latch operative to store a first bit associated with a first stored word;
forming a second latch, the second latch operative to store a second bit associated with a second stored word;
forming a first logic gate, the first logic gate being coupled to the first latch; and
forming a second logic gate, the second logic gate being coupled to the second latch;
wherein the first and second latches collectively comprise a plurality of latch transistors, each of the plurality of latch transistors comprising a respective channel, the channels being oriented in substantially the same direction; and
wherein the memory cell comprises a central portion in which the first and second latches are implemented, and first and second side portions arranged on opposite sides of the central portion, the first and second logic gates being implemented in the side portions.
12. An integrated circuit comprising a content-addressable memory, the content-addressable memory including a plurality of memory cells, at least one of the plurality of memory cells comprising:
a first latch, the first latch operative to store a first bit associated with a first stored word;
a second latch, the second latch operative to store a second bit associated with a second stored word;
a first logic gate, the first logic gate coupled to the first latch; and
a second logic gate, the second logic gate coupled to the second latch;
wherein the first and second latches collectively comprise a plurality of latch transistors, each of the plurality of latch transistors comprising a respective channel, the channels being oriented in substantially the same direction; and
wherein the memory cell comprises a central portion in which the first and second latches are implemented, and first and second side portions arranged on opposite sides of the central portion, the first and second logic gates being implemented in the side portions.
13. The integrated circuit of claim 12 , wherein at least one of the first and second logic gates comprises a vertical via that is shared with a different memory cell in the plurality of memory cells.
14. The integrated circuit of claim 13 , wherein the vertical via lands on a diffusion level.
15. The integrated circuit of claim 12 , wherein the content-addressable memory comprises four or more memory cells, the four or more memory cells arranged in an array having a plurality of rows and a plurality of columns, each of the plurality of rows operative to store two words.
16. The integrated circuit of claim 15 , wherein each of the plurality memory cells in a given row is coupled to two common word lines and to two common match lines.
17. The integrated circuit of claim 15 , wherein each of the plurality memory cells in a given column is coupled to two common search lines and to two common bit lines.
18. The integrated circuit of claim 12 , wherein the content-addressable memory is implemented with segmented bit lines.
19. An apparatus comprising a content-addressable memory, the content-addressable memory including a plurality of memory cells, at least one of the plurality of memory cells comprising:
a first latch, the first latch operative to store a first bit associated with a first stored word;
a second latch, the second latch operative to store a second bit associated with a second stored word;
a first logic gate, the first logic gate coupled to the first latch; and
a second logic gate, the second logic gate coupled to the second latch;
wherein the first and second latches collectively comprise a plurality of latch transistors, each of the plurality of latch transistors comprising a respective channel, the channels being oriented in substantially the same direction; and
wherein the memory cell comprises a central portion in which the first and second latches are implemented, and the first and second side portions arranged on opposite sides of the central portion, the first and second logic gates being implemented in the side portions.
20. The apparatus of claim 19 , wherein the apparatus comprises at least one of a data networking device, a memory mapping device, and a data compression device.