Magnetic memory

1. A magnetic memory, comprising:

a plurality of magnetoresistive elements which include a fixed layer in which a magnetization direction is fixed, a free layer in which a magnetization direction changes, and a nonmagnetic layer formed between the fixed layer and the free layer, and records data by a resistance value which changes on the basis of the magnetization direction of the free layer;

a word line electrically connected to first terminals of the magnetoresistive elements;

a plurality of bit lines electrically connected to second terminals of the magnetoresistive elements, respectively; and

a current controller configured to,

during data erase, supply a current to the word line to generate a magnetic field without supplying a current to the bit lines, set the magnetization direction of the free layer in a first direction by the magnetic field, and erase data of the magnetoresistive elements electrically connected to the word line by one time data erase, and

during data write, supply a current in one direction to each magnetoresistive element using the word line and the bit lines, and set the magnetization direction of the free layer in a second direction by spin transfer magnetization reversal.

2. The memory according to claim 1 , further comprising:

a plurality of diodes which are electrically connected between the second terminals of the magnetoresistive elements and the bit lines, and sets a direction of a current flowing through the magnetoresistive element.

3. The memory according to claim 2 , wherein

an anode of the diode is electrically connected to the magnetoresistive element, and

a cathode of the diode is electrically connected to the bit line.

4. The memory according to claim 2 , wherein

an anode of the diode is electrically connected to the bit line, and

a cathode of the diode is electrically connected to the magnetoresistive element.

5. The memory according to claim 2 , wherein the diodes are formed by stacking an n-type semiconductor layer and a p-type semiconductor layer.

6. The memory according to claim 5 , wherein the diodes and the magnetoresistive elements are stacked.

7. The memory according to claim 2 , wherein during data erase, the current controller reversely biases the diodes such that a current does not flow to the magnetoresistive elements.

8. The memory according to claim 2 , wherein during data write, the current controller reversely biases a diode electrically connected to a nonselected magnetoresistive element such that a current does not flow to the nonselected magnetoresistive element.

9. The memory according to claim 1 , wherein

the magnetoresistive elements include a plurality of first magnetoresistive elements and a plurality of second magnetoresistive elements,

the first magnetoresistive elements are arranged on one side of the word line,

the second magnetoresistive elements are arranged on the other side of the word line, and

the first magnetoresistive elements and the second magnetoresistive elements share the word line.

10. The memory according to claim 9 , wherein the second magnetoresistive elements are stacked on the first magnetoresistive elements via the word line.

11. The memory according to claim 10 , wherein the free layer is placed close to the word line.

12. The memory according to claim 1 , wherein the word line includes a metal layer and a magnetic layer covering the metal layer.

13. The memory according to claim 1 , further comprising:

a plurality of selection transistors electrically connected to the second terminals of the magnetoresistive elements, wherein

the bit lines are connected to gate terminals of the selection transistors, respectively.

14. The memory according to claim 13 , wherein source terminals of the selection transistors are grounded.

15. The memory according to claim 1 , wherein data of at least two magnetoresistive elements are written by one time data write.