Semiconductor memory device and test method thereof
View Patent ↗When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip.
1. A method of performing operational testing of a plurality of semiconductor memory devices, each having a data input and output terminal, a clock terminal, an address terminal, and a command terminal, in a state that the clock terminal, the address terminal, and the command terminal are connected in common among the plurality of semiconductor memory devices, wherein the test method comprises:
a first step of measuring a reference voltage generated inside the semiconductor memory device;
a second step of generating a code for temporarily adjusting the reference voltage, based on a result of measuring the reference voltage;
a third step of entering a test mode in which the semiconductor memory device is configured to receive any one of a clock signal, an address signal, and a command, from the data input and output terminal; and
a fourth step of supplying the code via the data input and output terminal or the address terminal, in the test mode.
2. The method of testing a semiconductor memory device as claimed in claim 1 , further comprising a fifth step of writing data to and reading data from the plurality of semiconductor memory devices, after performing the fourth step.
3. The method of testing a semiconductor memory device as claimed in claim 2 , further comprising a sixth step of writing data to a nonvolatile memory circuit for permanently adjusting the reference voltage, after performing the fifth step.
4. The method of testing a semiconductor memory device as claimed in claim 3 , wherein the nonvolatile memory circuit is a fuse circuit, and the fuse circuit is disconnected at the sixth step.
5. The method of testing a semiconductor memory device as claimed in claim 1 , wherein the plurality of semiconductor memory devices are formed on the same semiconductor wafer.
6. A method of performing operational testing of a plurality of semiconductor memory devices, each having a data input and output terminal, a clock terminal, an address terminal, and a command terminal, in a state that the clock terminal the address terminal, and the command terminal are connected in common among the plurality of semiconductor memory devices, wherein the test method comprises:
a first step of measuring a reference voltage generated inside the semiconductor memory device;
a second step of generating a code for temporarily adjusting the reference voltage, based on a result of measuring the reference voltage;
a third step of entering a test mode in which the semiconductor memory device is configured to receive any one of a clock signal, an address signal, and a command, from the data out put terminal; and
a fourth step of supplying the code via the data input and output terminal or the address terminal, in a state of entering the test mode,
wherein in the fourth step, the code is supplied in common to the plurality of semiconductor memory devices via the address terminal, the clock signal is selectively supplied to a part of the plurality of semiconductor memory devices via the data input and output terminal, and a supply of a clock signal to the clock terminal provided in the plurality of semiconductor memory devices is stopped.
7. The method of testing a semiconductor memory device as claimed in claim 6 , further comprising a fifth step of writing data to and reading data from the plurality of semiconductor memory devices, after performing the fourth step.
8. The method of testing a semiconductor memory device as claimed in claim 7 , further comprising a sixth step of writing data to a nonvolatile memory circuit for permanently adjusting the reference voltage, after performing the fifth step.
9. The method of testing a semiconductor memory device as claimed in claim 8 , wherein the nonvolatile memory circuit is a fuse circuit, and the fuse circuit is disconnected at the sixth step.
10. A method of testing of a plurality of semiconductor devices, each of the devices having a data input and output terminal, a clock terminal, an address terminal, and a command terminal, wherein the test method comprises:
executing a first test mode, in which the clock terminal, the address terminal, and the command terminal are connected in common among the plurality of devices, respectively, the data input and output terminal is not connected in common among the devices, and the devices are configured to control in common via the clock terminal, the address terminal, and the command terminal; and
executing a second test mode, in which the clock terminal, the address terminal, and the command terminal are connected in common among the plurality of devices, respectively, the data input and output terminal is not connected in common among the devices, a selected one or ones of the devices are configured to control via the data input and output terminal of each of the selected one or ones of the devices, and unselected one or ones of the device are configured not to control.
11. The method as claimed in claim 10 , wherein in the first test mode the devices are configured to receive a clock signal, an address signal, and a command in common; and in the second test mode the selected one or ones of the devices are configured to receive at least one of the clock signal, the address signal, and the command, and the unselected one or ones of the devices are configured not to receive at least one of the clock signal, the address signal, and the command.
12. The method as claimed in claim 10 , wherein in the second test mode the clock signal is supplied to the selected one or ones of the devices via the data input and output terminal of each of the selected one or ones of the devices and a supply of a clock signal to the one or ones of the devices via the clock terminal is stopped.
13. The method as claimed in claim 10 , wherein in the second test mode the address signal is supplied to the selected one or ones of the devices via the data input and output terminal of each of the selected one or ones of the devices and a supply of an address signal to the one or ones of the devices via the address terminal is stopped.
14. The method as claimed in claim 10 , wherein in the second test mode the command is supplied to the selected one or ones of the devices via the data input and output terminal of each of the selected one or ones of the devices and a supply of a command to the one or ones of the devices via the command terminal is stopped.
15. The method as claimed in claim 10 , wherein the first test mode and the second test mode are selected based on a predetermined code inputted to the device via the address terminal and command terminal of each of the devices.
16. The method as claimed in claim 10 , wherein the first test mode includes measuring a reference voltage generated inside each of the devices, and the second test mode includes supplying the selected one or ones of the devices with a predetermined code corresponding to the reference voltage of the selected one or ones of the devices.
17. The method as claimed in claim 10 , wherein the first test mode is a first step and the second test mode is a second step executed after the first step, and the method including a third step executed after the first step, wherein in the third step the devices are configured to control in common.
18. The method as claimed in claim 17 , wherein the first step includes measuring a reference voltage generated inside each of the devices, the second step includes supplying the selected one or ones of the devices with a predetermined code corresponding to the reference voltage of the selected one or ones of the devices, and the third step includes writing data to and reading data from the devices.