Chip-size package structure and method of the same
View Patent ↗The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.
1. A chip-size package structure, comprising:
a base;
a die with pads adhered to said base;
first conductive lines formed on said die to cover said pads;
a first dielectric layer formed on said die and said first conductive lines, and said first dielectric layer having first openings on said first conductive lines;
a first material layer formed on said base and filled in a space between said dice on said base;
a second dielectric layer formed on said first dielectric layer and said first material layer, and said second dielectric layer having second openings on said first conductive lines;
second conductive lines formed on said first openings and said second openings to electrically couple with said first conductive lines, respectively;
a second material layer formed on said second conductive lines and said second dielectric layer, and said second material layer having third openings on said second conductive lines; and
solder balls welded on said third openings and electrically coupling with said second conductive lines, respectively.
2. The package structure in claim 1 , wherein surfaces of said first dielectric layer and said first material layer are substantially at same level.
3. The package structure in claim 1 , wherein said die is formed by sawing a processed base.
4. The package structure in claim 3 , wherein said processed base is back lapped to get a thickness of said processed base around 200-400 μm.
5. The package structure in claim 1 , wherein materials of said first material layer and said second material layer comprise UV curing type material or heat curing type material.
6. The package structure in claim 5 , wherein said first material layer comprises silicon rubber, SINR, BCB or epoxy.
7. The package structure in claim 5 , wherein said second material layer comprises SINR, BCB, Solder mask (Epoxy).
8. The package structure in claim 1 , wherein said first conductive lines comprise Al, Ti, Cu, and the combination thereof.
9. The package structure in claim 1 , wherein said second conductive lines comprise Ti, Ni, Cu, Au, and the combination thereof.
10. The package structure in claim 1 , wherein said base comprises metal, alloy 42 (42Ni58Fe) or glass.
11. The package structure in claim 10 , wherein said metal comprises Fe, Co, Ni, and the combination thereof, and thickness of said metal is about 200-300 μm.
12. The package structure in claim 1 , wherein said first dielectric layer comprises BCB, SINR, PI or silicon rubber.
13. The package structure in claim 1 , wherein said second dielectric layer is silicon rubber, SINR, BCB.