IP Library Granted Patent US 7,524,742
Granted Patent B2
US 7,524,742 · App. 11/748,472 · Granted Apr 28, 2009

Structure of metal interconnect and fabrication method thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,524,742
App. No.
11/748,472
Granted
Apr 28, 2009
Kind
B2
Abstract

A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Claims (12)

1. A metal interconnect structure, the metal interconnect structure being positioned on a substrate, and at least a first electric conductor being positioned on the substrate, the metal interconnect structure comprising:

a first dielectric layer positioned on the substrate and covering the first electric conductor;

a first patterned hard mask positioned on the first dielectric layer;

a second electric conductor positioned in the first patterned hard mask and the first dielectric layer and electrically connected with the first electric conductor;

a second dielectric layer positioned on the first patterned hard mask and the second electric conductor; and

a third electric conductor positioned in the second dielectric layer and partially covering the first patterned hard mask and electrically connected with the second electric conductor.

2. The metal interconnect structure of claim 1 , wherein the first electric conductor includes a gate, a source, a drain, or a doped region.

3. The metal interconnect structure of claim 2 , wherein the second electric conductor is a contact plug.

4. The metal interconnect structure of claim 3 , wherein a contact etch stop layer (CESL) is positioned between the substrate and the first dielectric layer and covers the first electric conductor.

5. The metal interconnect structure of claim 1 , wherein the first electric conductor surface contains a silicide layer.

6. The metal interconnect structure of claim 5 , wherein the patterned hard mask layer includes a chemical compound of silicon with carbon or nitrogen.

7. The metal interconnect structure of claim 1 , wherein the third electric conductor includes a via plug or a metal line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2023
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 065294/0055 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2007
From: CHOU, PEI-YU; HUANG, CHUN-JEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 019292/0350 →