Clock switch for generation of multi-frequency clock signal
View Patent ↗An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.
1. A method for generating a multi-frequency clock signal, comprising:
receiving a first clock signal, a clock selection signal, and a feedback signal from a second clock selection circuit in a first clock selection circuit;
generating a first clock selection signal based on the state of the first clock signal, the clock selection signal, and the feedback signal;
receiving a second clock signal and the clock selection signal in the second clock selection circuit;
generating a second clock selection signal based only on the state of the second clock signal and the clock selection signal;
receiving the first clock signal, the second clock signal, the first clock selection signal and the second clock selection signal in a multiplexer; and
passing either the first clock signal or the second clock signal to a clock output based on the state of the first clock selection signal and the second clock selection signal;
wherein the first clock signal has a higher frequency than the second clock signal.
2. The method of claim 1 , wherein the first and second clock signals are asynchronous.
3. The method of claim 1 , wherein generating a first clock selection signal comprises gating the propagation of the clock selection signal based on the state of the feedback signal.
4. The method of claim 1 , wherein generating a first clock selection signal comprises latching the clock selection signal on a rising edge of the first clock signal.
5. The method of claim 4 , wherein generating a first clock selection signal further comprises latching the clock selection signal on a falling edge of the first clock signal.
6. The method of claim 1 , wherein generating a second clock selection signal comprises latching the clock selection signal on a rising edge of the second clock signal.
7. The method of claim 6 , wherein generating a second clock selection signal further comprises latching the clock selection signal on a falling edge of the second clock signal.
8. The method of claim 1 , wherein the clock selection signal and the second clock signal are synchronous and wherein generating a second clock selection signal comprises only latching the clock selection signal on a falling edge of the second clock signal.
9. A clock switch for generating a multi-frequency clock, comprising:
a first clock selection circuit configured to receive a first clock signal, a clock selection signal, and a feedback signal from a second clock selection circuit and to generate a first clock selection signal based on the state of the first clock signal, the clock selection signal, and the feedback signal;
a second clock selection circuit configured to receive a second clock signal and the clock selection signal and to generate a second clock selection signal based only on the state of the second clock signal and the clock selection signal; and
a clock selection multiplexer configured to receive the first clock signal, the second clock signal, the first clock selection signal and the second clock selection signal and to pass either the first clock signal or the second clock signal to a clock output based on the state of the first clock selection signal and the second clock selection signal;
wherein the first clock signal has a higher frequency than the second clock signal.
10. The clock switch of claim 9 , wherein the first and second clock signals are asynchronous.
11. The clock switch of claim 9 , wherein the first clock selection circuit includes a logic gate configured to gate the propagation of the clock selection signal based on the state of the feedback signal.
12. The clock switch of claim 9 , wherein the first clock selection circuit includes at least one flip-flop that is configured to latch the clock selection signal on a rising edge of the first clock signal.
13. The clock switch of claim 12 , wherein the first clock selection circuit further includes a flip-flop that is configured to latch the clock selection signal on a falling edge of the first clock signal.
14. The clock switch of claim 9 , wherein the second clock selection circuit includes at least one flip-flop that is configured to latch the clock selection signal on a rising edge of the second clock signal.
15. The clock switch of claim 14 , wherein the second clock selection circuit further includes a flip-flop that is configured to latch the clock selection signal on a falling edge of the second clock signal.
16. The clock switch of claim 9 , wherein the clock selection signal and the second clock signal are synchronous and wherein the second clock selection circuit consists of a flip-flop that is configured to latch the clock selection signal on a falling edge of the second clock signal.
17. A system for generating a multi-frequency clock signal, comprising:
a first clock source configured to generate a first clock signal;
a second clock source configured to generate a second clock signal that has a lower frequency than the first clock signal; and
a clock switch circuit, including:
a first clock selection circuit configured to receive the first clock signal, a clock selection signal, and a feedback signal from a second clock selection circuit and to generate a first clock selection signal based on the state of the first clock signal, the clock selection signal, and the feedback signal;
a second clock selection circuit configured to receive the second clock signal and the clock selection signal and to generate a second clock selection signal based only on the state of the second clock signal and the clock selection signal; and
a clock selection multiplexer configured to receive the first clock signal, the second clock signal, the first clock selection signal and the second clock selection signal and to pass either the first clock signal or the second clock signal to a clock output based on the state of the first clock selection signal and the second clock selection signal.
18. The system of claim 17 , wherein the first and second clock signals are asynchronous.
19. The system of claim 17 , wherein the first clock selection circuit includes a logic gate configured to gate the propagation of the clock selection signal based on the state of the feedback signal.
20. The system of claim 17 , wherein the first clock selection circuit includes at least one flip-flop that is configured to latch the clock selection signal on a rising edge of the first clock signal.
21. The system of claim 20 , wherein the first clock selection circuit further includes a flip-flop that is configured to latch the clock selection signal on a falling edge of the first clock signal.
22. The system of claim 17 , wherein the second clock selection circuit includes at least one flip-flop that is configured to latch the clock selection signal on a rising edge of the second clock signal.
23. The system of claim 17 , wherein the second clock selection circuit further includes a flip-flop that is configured to latch the clock selection signal on a falling edge of the second clock signal.
24. The system of claim 17 , wherein the clock selection signal and the second clock signal are synchronous and wherein the second clock selection circuit consists of a flip-flop that is configured to latch the clock selection signal on a falling edge of the second clock signal.