Resistance variable memory cells
View Patent ↗An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.
1. A memory cell comprising:
a first line over a substrate, the first line comprising a first conductive material;
a second conductive material in contact with at least a portion of the first conductive material, the second conductive material being different from the first conductive material;
a chalcogenide material in contact with at least a portion of the second conductive material and completely separated from the first conductive material; and
a second line over at least a portion of the chalcogenide material, the second line comprising a third conductive material.
2. The memory cell of claim 1 , wherein the chalcogenide material comprises a conductive pathway and wherein the conductive pathway is at a lateral edge of the chalcogenide material.
3. The memory cell of claim 1 , wherein the third conductive material is in contact with at least a portion of the chalcogenide material.
4. The memory cell of claim 1 , wherein the second conductive material is an immersion plated layer.
5. The memory cell of claim 1 , wherein the second conductive material comprises silver.
6. The memory cell of claim 1 , wherein the chalcogenide material comprises germanium selenide having ions of the second conductive material therein.
7. The memory cell of claim 1 , wherein the second conductive material and the chalcogenide material are disposed within a dielectric material.
8. The memory cell of claim 1 , wherein the chalcogenide material is capable of changing resistance in response to a voltage applied thereto.
9. The memory cell of claim 1 , wherein the first conductive material comprises one of aluminum, copper, nickel and tungsten.
10. A memory device comprising:
a memory array comprising a plurality of memory cells, at least one memory cell comprising:
a first line over a substrate, the first line comprising a first conductive material;
a second conductive material in contact with at least a portion of the first conductive material, the second conductive material being different from the first conductive material;
a chalcogenide material in contact with at least a portion of the second conductive material and completely separated from the first conductive material; and
a second line in contact with at least a portion of the chalcogenide material, the second line comprising a third conductive material.
11. The memory device of claim 10 , wherein the second conductive material comprises silver.
12. The memory device of claim 10 , wherein the chalcogenide material comprises germanium selenide having ions of the second conductive material therein.
13. The memory device of claim 10 , wherein the second conductive material and the chalcogenide material are disposed within a dielectric material.
14. The memory device of claim 10 , wherein the second conductive material has a thickness between about 500 Angstroms to about 2000 Angstroms.
15. The memory device of claim 10 , wherein the chalcogenide material has a thickness between about 200 Angstroms to about 800 Angstroms.
16. The memory device of claim 10 , wherein the chalcogenide material has an upper surface and a lateral surface and wherein the third conductive material is in contact with at least a portion of the lateral surface of the chalcogenide material.