Metal-oxide-semiconductor transistor and method of forming the same
View Patent ↗A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has a gate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.
1. A MOS (metal-oxide-semiconductor) transistor, comprising:
a semiconductor substrate;
a gate structure positioned on the semiconductor substrate;
a source region positioned in the semiconductor substrate;
a drain region positioned in the semiconductor substrate;
a channel region disposed in the semiconductor substrate under the gate structure, positioned between the source region and the drain region;
a stress buffer layer covering the gate structure, the source region and the drain region; and
a stressed cap layer covering the stress buffer layer, and a tensile stress of the stressed cap layer being larger than a tensile stress of the stress buffer layer.
2. The MOS transistor according to claim 1 , wherein the MOS transistor is an NMOS transistor or a PMOS transistor.
3. The MOS transistor according to claim 1 , wherein the gate structure comprises:
a gate dielectric layer positioned on the semiconductor substrate;
a gate positioned on the gate dielectric layer; and
a spacer adjacent to a sidewall of the gate.
4. The MOS transistor according to claim 1 , wherein the gate structure comprises:
a gate dielectric layer positioned on the semiconductor substrate; and
a gate without a spacer, positioned on the gate dielectric layer.
5. The MOS transistor according to claim 1 , wherein a thickness of the stress buffer layer is in a range from 10 to 300 angstroms.
6. The MOS transistor according to claim 1 , wherein the tensile stress of the stress buffer layer is smaller than 1.52 GPa.
7. The MOS transistor according to claim 1 , wherein the stressed cap layer comprises a silicon nitride layer.
8. The MOS transistor according to claim 1 , wherein the stressed cap layer comprises a multiple-layer structure.
9. The MOS transistor according to claim 1 , wherein the tensile stress of the stressed cap layer decreases from top to bottom gradually.
10. The MOS transistor according to claim 1 , wherein a ratio of a thickness of the stress buffer layer to a thickness of the stressed cap layer is smaller than 0.5.
11. The MOS transistor according to claim 1 , wherein the stress buffer layer comprises a silicon oxide layer.
12. The MOS transistor according to claim 1 , wherein the stress buffer layer comprises a silicon nitride layer.
13. The MOS transistor according to claim 12 , further comprising a silicon oxide layer positioned under the stress buffer layer, wherein the silicon oxide layer covers the gate structure, the source region and the drain region.