Wirebond pad for semiconductor chip or wafer

1. A process for fabricating a semiconductor chip comprising:

providing a semiconductor substrate, a dielectric layer over said semiconductor substrate, a copper layer over said semiconductor substrate and in said dielectric layer, wherein said copper layer has a top surface substantially coplanar with a top surface of said dielectric layer, and a separating layer over said semiconductor substrate, on said top surface of said dielectric layer and on said top surface of said copper layer, wherein an opening in said separating layer is over a contact point of said top surface of said copper layer, and said contact point is at a bottom of said opening, wherein said separating layer comprises a nitride;

forming a titanium-containing layer over said contact point and said separating layer;

forming a first gold layer on said titanium-containing layer;

after said forming said first gold layer, forming a resist layer;

after said forming said resist layer, electroplating a second gold layer with a thickness between 2 and 20 micrometers over said first gold layer;

after said electroplating said second gold layer, removing said resist layer; and

after said removing said resist layer, removing said titanium-containing layer not under said second gold layer.

2. The process of claim 1 further comprising providing an aluminum-containing layer over said copper layer, followed by said forming said titanium-containing layer further over said aluminum-containing layer.

3. The process of claim 1 , wherein said separating layer further comprises an oxide.

4. The process of claim 1 , wherein said nitride has a thickness greater than 0.3 micrometers.

5. The process of claim 1 , after said removing said titanium-containing layer not under said second gold layer, further comprising bonding a wire to said second gold layer.

6. A process for fabricating a semiconductor chip comprising:

providing a semiconductor substrate, a dielectric layer over said semiconductor substrate, a copper layer over said semiconductor substrate and in said dielectric layer, wherein said copper layer has a top surface substantially coplanar with a top surface of said dielectric layer, a separating layer over said semiconductor substrate, on said top surface of said dielectric layer and on said top surface of said copper layer, wherein an opening in said separating layer is over a contact point of said top surface of said copper layer, and said contact point is at a bottom of said opening, wherein said separating layer comprises a nitride, and an aluminum-containing layer connected to said contact point through said opening; and

forming a wirebonding pad connected to said aluminum-containing layer, wherein said forming said wirebonding pad comprises forming a first metal layer over said aluminum-containing layer and said separating layer, next forming a resist layer, next forming a second metal layer over said first metal layer, next removing said resist layer, and then removing said first metal layer not under said second metal layer.

7. The process of claim 6 further comprising said forming said wirebonding pad vertically over said aluminum-containing layer.

8. The process of claim 6 , wherein said forming said wirebonding pad, after said forming said first metal layer, further comprises forming a third metal layer over said first metal layer, followed by said forming said resist layer.

9. The process of claim 6 , wherein said forming said second metal layer comprises an electroplating process.

10. The process of claim 6 , wherein said forming said first metal layer comprises forming a titanium-containing layer over said aluminum-containing layer and said separating layer.

11. The process of claim 6 , wherein said forming said second metal layer comprises forming a gold layer with a thickness between 2 and 20 micrometers over said first metal layer.

12. The process of claim 6 , wherein said separating layer further comprises an oxide.

13. The process of claim 6 , wherein said nitride has a thickness greater than 0.3 micrometers.

14. The process of claim 6 , after said forming said wirebonding pad, further comprising bonding a wire to said second metal layer.

15. A process for fabricating a semiconductor chip or wafer comprising:

providing a semiconductor substrate, a dielectric layer over said semiconductor substrate, a copper layer over said semiconductor substrate and in said dielectric layer, wherein said copper layer has a top surface substantially coplanar with a top surface of said dielectric layer, a separating layer over said semiconductor substrate, on said top surface of said dielectric layer and on said top surface of said copper layer, wherein an opening in said separating layer is over a contact point of said top surface of said copper layer, and said contact point is at a bottom of said opening, wherein said separating layer comprises a nitride, and an aluminum-containing layer connected to said contact point through said opening;

forming a first metal layer over said aluminum-containing layer and said separating layer;

after said forming said first metal layer, forming a resist layer;

after said forming said resist layer, forming a gold layer over said first metal layer;

after said forming said gold layer, removing said resist layer; and

after said removing said resist layer, removing said first metal layer not under said gold layer.

16. The process of claim 15 , after said forming said first metal layer, further comprising forming a second metal layer over said first metal layer, followed by said forming said resist layer.

17. The process of claim 15 , wherein said forming said gold layer comprises an electroplating process.

18. The process of claim 15 , wherein said forming said first metal layer comprises forming a titanium-containing layer over said aluminum-containing layer and said separating layer.

19. The process of claim 15 further comprising said forming said gold layer with a thickness between 2 and 20 micrometers.

20. The process of claim 15 further comprising said forming said gold layer vertically over said aluminum-containing layer.

21. The process of claim 15 , wherein said nitride has a thickness greater than 0.3 micrometers.

22. The process of claim 15 , after said removing said first metal layer not under said gold layer, further comprising bonding a wire to said gold layer.

23. A semiconductor chip comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a copper layer over said semiconductor substrate and in said dielectric layer, wherein said copper layer has a top surface substantially coplanar with a top surface of said dielectric layer;

a separating layer over said semiconductor substrate, on said top surface of said dielectric layer and on said top surface of said copper layer, wherein an opening in said separating layer is over a contact point of said top surface of said copper layer, and said contact point is at a bottom of said opening, wherein said separating layer comprises a nitride;

an aluminum-containing layer connected to said contact point through said opening;

a first gold layer over said aluminum-containing layer, wherein said first gold layer has a thickness between 2 and 20 micrometers; and

a titanium-containing layer between said first gold layer and said aluminum-containing layer.

24. The semiconductor chip of claim 23 , wherein said nitride has a thickness greater than 0.3 micrometers.

25. The semiconductor chip of claim 23 , wherein said first gold layer is configured to have a wire bonded thereon.

26. The semiconductor chip of claim 23 further comprising a second gold layer under said first gold layer and over said titanium-containing layer.

27. The semiconductor chip of claim 23 , wherein said separating layer further comprises an oxide.