Method for manufacturing probe structure of probe card
View Patent ↗A method for manufacturing a probe structure of a probe card is disclosed. In accordance with the method of the present invention, a dual etching process of a silicon substrate or an etching process of an SOI substrates is carried out using a sidewall insulating film pattern as an etching mask to facilitate a formation of a bump and microscopic probe structure of the probe card.
1. A method for manufacturing a probe structure, the method comprising steps of:
(a) forming a first mask layer pattern defining a probe beam region on a semiconductor substrate;
(b) forming a second mask layer pattern defining a probe tip region on the semiconductor substrate and the first mask layer pattern;
(c) etching the semiconductor substrate using the second mask layer pattern as an etching mask to form the probe tip region;
(d) removing the second mask layer pattern;
(e) etching the semiconductor substrate using the first mask layer pattern as the etching mask to form the probe beam region;
(f) forming a sidewall insulating film pattern on a sidewall of each of the probe tip region and the probe beam region;
(g) etching a predetermined thickness of a portion of the semiconductor substrate exposed by the first mask layer pattern;
(h) removing the sidewall insulating film pattern and the first mask layer pattern; and
(i) forming a probe tip and a probe beam in the probe tip region and the probe beam region.
2. The method in accordance with claim 1 , wherein the semiconductor substrate comprises an SOI substrate.
3. The method in accordance with claim 2 , wherein the step (c) comprises etching an oxide film of the SOI substrate until a silicon layer under the oxide film is exposed.
4. The method in accordance with claim 2 , wherein the step (e) comprises etching an oxide film of the SOI substrate until a silicon layer under the oxide film is exposed.
5. The method in accordance with claim 2 , wherein the step (h) further comprises removing an oxide film of the SOI substrate.
6. The method in accordance with claim 1 , wherein the first mask layer pattern and the second mask layer pattern comprise a CVD TEOS film, respectively.
7. The method in accordance with claim 1 , wherein the step (g) is carried out using a KOH solution and a TMAH solution.
8. The method in accordance with claim 1 , wherein the step (i) comprises an electroplating process.
9. The method in accordance with claim 1 , wherein the probe tip and the probe beam of the step (i) comprise a Ni—Co layer, respectively.
10. The method in accordance with claim 1 , wherein the step (i) comprises:
forming a seed layer on the semiconductor substrate;
forming a dummy mask layer pattern exposing the probe tip region and the probe beam region; and
forming the probe tip and the probe beam in the probe tip region and the probe beam region, respectively.
11. The method in accordance with claim 10 , wherein the seed layer comprises a Ti/Cu layer.
12. The method in accordance with claim 1 , after carrying out the step (i), further comprising:
forming a photoresist film pattern exposing a region where a conductive bump is to be formed;
forming the conductive bump in the region where the conductive bump is to be formed; and
removing the photoresist film pattern.
13. The method in accordance with claim 1 , wherein the step (f) comprises:
forming an insulating film on the portion of the semiconductor substrate exposed by the first mask layer pattern; and
anisotropically etching the insulating layer until a surface of the semiconductor substrate is exposed to form the sidewall insulating film pattern on the sidewall of each of the probe tip region and the probe beam region.