Low pass filter low drop-out voltage regulator
View Patent ↗A low dropout voltage regulator is described having a pass device, differential amplifiers, and a feedback loop including a low pass filter. Two differential amplifiers arranged in parallel coupled to the low pass filter in the feedback loop provide a specified and stable DC voltage whose input-to-output voltage difference is low. Improved stability, reduced die area, improved power supply rejection ratio, increased bandwidth, decreased power consumption, and better electrostatic discharge (ESD) protection may result.
1. A low drop-out voltage comprising:
a first differential amplifier, wherein a reference signal is coupled to a non-inverting input of the first differential amplifier;
a second differential amplifier arranged in parallel with the first differential amplifier; and
a feedback loop of the low drop-out voltage regulator, comprising:
a voltage divider operable to produce a first feedback signal, wherein the first feedback signal is coupled to an inverting input of the first differential amplifier, an inverting input of the second differential amplifier, and a low pass filter; and
the low pass filter operable to produce a second feedback signal, wherein the second feedback signal is coupled to a non-inverting input of the second differential amplifier.
2. The low drop-out voltage regulator of claim 1 , further comprising a pass device coupled with the first differential amplifier, the second differential amplifier, and the feedback loop; and wherein the pass device is operable to produce a controlled output voltage.
3. The low drop-out voltage regulator of claim 2 , wherein the pass device comprises a PMOS transistor.
4. The low drop-out voltage regulator of claim 2 , further comprising an interstage amplifier positioned prior to the pass device and positioned after the first and second differential amplifiers.
5. The low drop-out voltage regulator of claim 4 , wherein the interstage amplifier comprises an NMOS transistor coupled to ground and the pass device; and a resistor coupled to the NMOS transistor and the pass device.
6. The low drop-out voltage regulator of claim 1 , wherein the first and second differential amplifiers comprise one or more PMOS transistors and one or more NMOS transistors.
7. A low drop-out voltage regulator, comprising:
a pass circuit operable to generate a controlled output voltage;
a differential amplifier coupled to the pass circuit, a reference signal, and a feedback signal, the differential amplifier operable to compare the reference signal and the feedback signal; and
a feedback circuit coupled to the pass circuit and the differential amplifier, the feedback circuit operable to generate the feedback signal and comprising:
a voltage divider;
a low pass filter;
a first feedback loop coupled between an output of the pass circuit and the differential amplifier, the first feedback loop comprising the voltage divider; and
a second feedback loop coupled between the output of the pass circuit and the differential amplifier, the second feedback loop comprising the voltage divider and the low pass filter.
8. The low drop-out voltage regulator of claim 7 , wherein the differential amplifier comprises one or more NMOS transistors and one or more PMOS transistors.
9. The low drop-out voltage regulator of claim 7 , wherein the pass circuit comprises a PMOS transistor.
10. The low drop-out voltage regulator of claim 7 , further comprising an interstage amplifier positioned prior to the pass circuit and positioned after the differential amplifier.
11. The low drop-out voltage regulator of claim 10 , wherein the interstage amplifier comprises an NMOS transistor coupled to ground and the pass circuit; and a resistor coupled to the NMOS transistor and the pass circuit.
12. The low drop-out voltage regulator of claim 7 , wherein the differential amplifier comprises one or more PMOS transistors and one or more NMOS transistors.
13. The low drop-out voltage regulator of claim 7 , wherein the differential amplifier comprises:
a first differential amplifier, wherein the reference signal is coupled to a non-inverting input of the first differential amplifier; and
a second differential amplifier arranged in parallel with the first differential amplifier.
14. The low drop-out voltage regulator of claim 7 , wherein the differential amplifier comprises:
a first differential amplifier, wherein the reference signal is coupled to a non-inverting input of the first differential amplifier; and
a second differential amplifier arranged in parallel with the first differential amplifier, wherein the reference signal is coupled to an inverting input of the second differential amplifier.
15. A low drop-out voltage regulator comprising:
a first differential amplifier, wherein a reference signal is coupled to a non-inverting input of the first differential amplifier;
a second differential amplifier arranged in parallel with the first differential amplifier, wherein the reference signal is coupled to an inverting input of the second differential amplifier; and
a feedback loop of the low drop-out voltage regulator, comprising:
a voltage divider operable to produce a first feedback signal, wherein the first feedback signal is coupled to an inverting input of the first differential amplifier and a low pass filter; and
the low pass filter operable to produce a second feedback signal, wherein the second feedback signal is coupled to a non-inverting input of the second differential amplifier.
16. The low drop-out voltage regulator of claim 15 , further comprising a pass device coupled with the first differential amplifier, the second differential amplifier, and the feedback loop; and wherein the pass device is operable to produce a controlled output voltage.
17. The low drop-out voltage regulator of claim 16 , wherein the pass device comprises a PMOS transistor.
18. The low drop-out voltage regulator of claim 16 , further comprising an interstage amplifier positioned prior to the pass device and positioned after the first and second differential amplifiers.
19. The low drop-out voltage regulator of claim 18 , wherein the interstage amplifier comprises an NMOS transistor coupled to ground and the pass device; and a resistor coupled to the NMOS transistor and the pass device.
20. The low drop-out voltage regulator of claim 15 , wherein the first and second differential amplifiers comprise one or more PMOS transistors and one or more NMOS transistors.