Page buffer for nonvolatile memory device
View Patent ↗A nonvolatile memory device implements a program routine followed by a program-verify routine when recording or modifying stored data. The nonvolatile memory device may include an array of memory cells for storing data, a sense node, and a gating circuit for selectively connecting a bitline of the array of memory cells to the sense node. The nonvolatile memory device may also include a page buffer coupled to the sense node. The page buffer may include a main latch for storing data to be written in the nonvolatile memory device, a cache latch for storing data supplied on an input line of the nonvolatile memory device to be transferred in the main latch through a source liner and a temporary static latch connected to the main latch through the source line and to the cache latch through an auxiliary switch and for transferring data between the main latch and the cache latch. The cache latch may be isolated from the source line during execution of the program routine and of the program-verify routine.
1. A nonvolatile memory device comprising:
an array of memory cells to store data;
a sense node; and
a page buffer coupled to said sense node and comprising
a main latch to store data to be written into said array of memory cells,
a cache latch to store data supplied on an input line of the nonvolatile memory device and to be transferred to said main latch,
an auxiliary switch,
a source line, and
a temporary latch coupled to said main latch through said source line and to said cache latch through said auxiliary switch, the temporary latch to transfer data between said main latch and said cache latch; said cache latch to be isolated from said source line during execution of a program routine and a program-verify routine of the nonvolatile memory device and to be coupled to said source line during execution of a read routine of the nonvolatile memory device.
2. The nonvolatile memory device according to claim 1 wherein said cache latch is configurable to upload a new page of data to be stored in said array of memory cells during transfer of data from said temporary latch to said main latch.
3. The nonvolatile memory device according to claim 1 wherein said main latch is configurable to be reset by refreshing its content and re-transferring the content from said cache latch through said temporary latch before execution of the program-verify routine.
4. The nonvolatile memory device according to claim 1 wherein said array of memory cells comprises FLASH memory cells.
5. A page buffer comprising:
a main latch;
a cache latch for storing input data to be transferred to said main latch;
a source line;
an auxiliary switch; and
a temporary latch coupled to said main latch through said source line and coupled to said cache latch through said auxiliary switch for transferring data between said main latch and said cache latch; said cache latch being isolated from said source line during execution of a program routine and a program- verify routine.
6. The page buffer according to claim 5 wherein said cache latch is configurable to upload a new page of data to be stored in an array of memory cells during transfer of data from said temporary latch to said main latch.
7. The page buffer according to claim 6 wherein said array of memory cells comprises FLASH memory cells.
8. The page buffer according to claim 5 wherein said main latch is configurable to be reset by refreshing its content and by re-transferring the content from said cache latch through said temporary latch before execution of the program-verify routine.
9. A method of operating a page buffer of a nonvolatile memory device having an array of memory cells to implement a program routine followed by a program-verify routine, the method comprising:
storing input data in a cache latch;
transferring data between the main latch and the cache latch through a temporary latch coupled to the main latch through a source line and coupled to the cache latch through an auxiliary switch;
isolating the cache latch from the source line during execution of the program routine and the program-verify routine; and
coupling the cache latch to the source line during execution of a read routine.
10. The method of operating a page buffer according to claim 9 further comprising configuring the cache latch to upload a new page of data to be stored in the array of memory cells during transfer of data from the temporary latch to the main latch.
11. The method of operating a page buffer according to claim 9 further comprising configuring the main latch for being reset by refreshing its content and by re-transferring the content from the cache latch through the temporary latch before execution of the program-verify routine.
12. The method of operating a page buffer according to claim 9 further comprising isolating the stored data in the cache latch from noise and voltage surges on the source line.
13. The method of operating a page buffer according to claim 9 wherein the array of memory cells comprises FLASH memory cells.
14. A method of operating a page buffer of a nonvolatile memory device comprising:
storing input data in a cache latch;
transferring data to a main latch from the cache latch through a temporary latch coupled to the main latch through a source line and coupled to the cache latch through an auxiliary switch, while isolating the cache latch from the source line during execution of a program routine and a program-verify routine; and
coupling the cache latch to the source line and transferring data to the cache latch through the source line during execution of a read routine.
15. The method of operating a page buffer according to claim 14 wherein the nonvolatile memory device comprises an array of memory cells; and further comprising configuring the cache latch to upload a new page of data to be stored in the array of memory cells during transfer of data from the temporary latch to the main latch.
16. The method of operating a page buffer according to claim 15 wherein the array of memory cells comprises FLASH memory cells.
17. The method of operating a page buffer according to claim 14 further comprising configuring the main latch for being reset by refreshing its content and by re-transferring the content from the cache latch through the temporary latch before execution of the program-verify routine.
18. The method of operating a page buffer according to claim 14 further comprising isolating the stored data in the cache latch from noise and voltage surges on the source line.