IP Library › Granted Patent US 7,684,256
Granted Patent B2
US 7,684,256 · App. 11/759,908 · Granted Mar 23, 2010

Flash memory device and program method

Assignee: Hynix Semiconductor Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,684,256
App. No.
11/759,908
Granted
Mar 23, 2010
Kind
B2
Abstract

A method for programming a flash memory device includes selecting bit lines connected to a plurality of memory strings and selecting a word line. A lower bit is programmed into the memory cells connected to the selected word line and programming a upper bit into the memory cells. The step of selecting the word line and the step of programming the upper bit are repeated.

Claims (25)

1. A flash memory device comprising:

a first memory group having a plurality of memory strings;

a second memory group having the same structure as that of the first memory group; and

a page buffer group having the same number of page buffers as the number of the memory strings of the first memory group or the number of memory strings of the second memory group, wherein one memory string of the first memory group and one memory string of the second memory group are oppositely connected to a corresponding page buffer of the page buffer group;

a plurality of first switching elements respectively connected to the plurality of memory strings in the first memory group, wherein the first switching elements are configured to supply a power supply voltage to the plurality of the memory strings in the first memory group according to a first signal;

a plurality of second switching elements connected between the page buffer group and the plurality of memory strings in the first memory group, wherein the second switching elements are configured to turned on or off in response to a second signal;

a plurality of third switching elements respectively connected to the plurality of memory strings in the second memory group, wherein the third switching elements are configured to supply the power supply voltage to the plurality of memory strings in the second memory group according to a third signal; and

a plurality of fourth switching elements connected between the page buffer group and the plurality of memory strings in the second memory group, wherein the fourth switching elements are configured to turned on or off in response to a fourth signal.

2. The flash memory device of claim 1 , wherein each of the first to fourth switching elements comprises an NMOS transistor.

3. A program method of a flash memory device, comprising the steps of:

providing a flash memory device including:

a first memory group having a plurality of memory strings,

a second memory group having the same structure as that of the first memory group,

a page buffer group having the same number of page buffers as the number of memory strings of the first memory group or the number of memory strings of the second memory group, wherein one memory string of the first memory group and one memory string of the second memory group are oppositely connected to a corresponding page buffer of the page buffer group,

a plurality of first switching elements respectively connected to the plurality of memory strings in the first memory group, wherein the first switching elements are configured to supply a power supply voltage to the plurality of the memory strings in the first memory group according to a first signal,

a plurality of second switching elements connected between the page buffer group and the plurality of memory strings in the first memory group, wherein the second switching elements are configured to turned on or off in response to a second signal,

a plurality of third switching elements respectively connected to the plurality of memory strings in the second memory group, wherein the third switching elements are configured to supply the power supply voltage to the plurality of memory strings in the second memory group according to a third signal, and

a plurality of fourth switching elements connected between the page buffer group and the plurality of memory strings in the second memory group, wherein the fourth switching elements are configured to turned on or off in response to a fourth signal;

selecting bit lines connected to the plurality of memory strings in the first memory group or the plurality of memory strings in the second memory group through the second and fourth switching elements;

selecting a word line of the first memory group or the second memory group; and

performing a programming operation.

4. The program method of the flash memory device of claim 1 , wherein the memory strings of the first memory group are each connected to an even bit line and the memory strings of the second memory group are each connected an odd bit line.

5. The program method of the flash memory device of claim 3 , wherein the programming operation comprises the steps of:

programming a lower bit of the selected word line; and

programming an upper bit of the selected word line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2007
From: KIM, KI SEOG
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 019586/0161 →
Priority Claims (1)
KR 10-2006-0096099 · Sep 29, 2006 · national
Continuity (1)
Related Publication 20080080236A1 · Apr 3, 2008