Semiconductor device having a sense amplifier
View Patent ↗A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutually related to each other so that the drain of one transistor is connected to the gate of the other transistor. The gate of the first transistor and the gate of the second transistor are offset in the row direction. The first transistor and the second transistor are in a diagonal positional relationship.
1. A semiconductor device comprising a plurality of pair transistors each including a first transistor and a second transistor, the pair transistors being arrayed in a repeating pattern in a row direction, wherein
a drain of the first transistor is connected to a gate of the second transistor;
a drain of the second transistor is connected to a gate of the first transistor; and
the gates of the pair transistors are in a diagonal positional relationship to each other so that the pair transistors are offset in the row direction and a column direction such that the positions of said pair transistors are shifted in the row direction so as to not overlap in the row direction and said pair transistors are shifted in the column direction so as to only partially overlap in the column direction.
2. The semiconductor device as claimed in claim 1 , wherein the shortest distance between the gates of the pair transistors is set to be the minimum feature size.
3. The semiconductor device as claimed in claim 1 , wherein the pair transistors adjacent in the row direction are in an axially symmetric relationship with respect to an axis in the column direction permitting a balanced design in terms of resistance and capacitance with respect to a pair of bit lines.
4. The semiconductor device as claimed in claim 1 , wherein the pair transistors are MOS transistors, and the gates thereof are ring-shaped.
5. The semiconductor device as claimed in claim 1 , wherein the pair transistors are MOS transistors, and the gates thereof are U-shaped.
6. The semiconductor device as claimed in claim 1 , further comprising a pair of bit lines including first and second bit lines extending in the column direction, wherein
the drain of the first transistor is connected to the gate of the second transistor via the first bit line; and
the drain of the second transistor is connected to the gate of the first transistor via the second bit line.
7. The semiconductor device as claimed in claim 1 , wherein the pair transistors are disposed in striped active regions extending in the row direction.
8. The semiconductor device as claimed in claim 1 , wherein groups of pair transistors are arrayed in a repeating pattern in the row direction are disposed in multiple steps in the column direction.
9. The semiconductor device as claimed in claim 1 , comprising:
a first group of pair transistors in which the pair transistors are arrayed in a repeating pattern in the row direction, and
a second group of pair transistors adjacently disposed in the column direction with respect to first group of pair transistors, wherein
the pattern of the first group of pair transistors and the pattern of the second group of pair transistors are positionally related so as to be offset substantially by a single transistor in the row direction.
10. A semiconductor device, comprising:
a first bit line pair extending in a column direction;
a first active region extending in a row direction; and
first and second transistors that are formed in the first active region and that amplify a difference in electric potential between the first bit line pair, wherein
gate electrodes of the first and second transistors both have a curved portion and are in a diagonal positional relationship to each other so that said first and second transistors are offset in the row direction and a column direction such that the positions of said first and second transistors are shifted in the row direction so as to not overlap in the row direction and said first and second transistors are shifted in the column direction so as to only partially overlap in the column direction.
11. The semiconductor device as claimed in claim 10 , further comprising:
a second bit line pair disposed adjacent to the first bit line pair in the row direction;
a second active region disposed adjacent to the first active region in the column direction; and
third and fourth transistors that are formed in the second active region and that amplify a difference in electric potential between the second bit line pair, wherein
gate electrodes of the third and fourth transistors both have a curved portion and are in a diagonal positional relationship to each other so that said first and second transistors are offset in the row direction and a column direction such that the positions of said first and second transistors are shifted in the row direction so as to not overlap in the row direction and said first and second transistors are shifted in the column direction so as to only partially overlap in the column direction.
12. A semiconductor device comprising:
a plurality of pairs of bit lines, each of the pairs of bit lines including first and second hit lines each extending in a first direction, the pairs of bit lines being arranged in a second direction perpendicular to the first direction; and
a plurality of pairs of transistors, each of the pairs of the transistors including first and second transistors provided correspondingly to the first and second bit lines of an associated one of the pairs of bit lines, the first transistor having a gate and a drain coupled respectively to a drain and a gate of the second transistor, the gate of the first transistor being in a diagonal relationship with the gate of the second transistor such that the first transistor is offset in both of the first and second directions with respect to the gate of the second transistor while respective potions of the gates of the first and second transistors are shifted in the first direction so as to not overlap in the first direction and said pair transistors are shifted in the second direction so as to only partially overlap in the second direction.
13. The semiconductor device as claimed in claim 12 , wherein the drain of the first transistor is coupled to the gate of the second transistor through a part of the first bit line, and the drain of the second transistor is coupled to the gate of the first transistor through a part of the second bit line.
14. The semiconductor device as claimed in claim 12 , further comprising an active region defined by an insulating region, the active region extending in the second direction to accommodate the pairs of transistors.
15. The semiconductor device as claimed in claim 14 , wherein each of the gates of the first and second transistors in each of the pairs of transistors being elongated over the insulating region beyond the active region to provide an elongated portion, and the semiconductor device further comprises a plurality of first contact plugs and a plurality of second contact plugs, each of the first contact plugs being connected to the elongated one of a corresponding one of the first transistors and each of the second contact plugs being connected to the elongated one of a corresponding one of the second transistors.
16. The semiconductor device as claimed in claim 12 , further comprising first and second active regions isolated from each other and arranged in the first direction, each of the first and second active regions being elongated in the second direction, the pairs of transistors being divided into first and second groups, the pairs of transistors belonging to the first group being arranged in the first active region in the second direction, and the pairs of transistors belonging to the second group being arranged in the second active region in the second direction.
17. The semiconductor device as claimed in claim 12 , further comprising first and second active regions isolated from each other and arranged in the first direction, each of the first and second active regions being elongated in the second direction, odd-numbered ones of the pairs of transistors being arranged in the first active region in the second direction and even-numbered ones of the pairs of transistors being arranged in the second active region in the second direction such that the gate of the second transistor of the odd-numbered ones of the pairs of transistors is substantially equal in position in the second direction to the gate of the first transistor of the even-numbered ones of the pairs of transistors.
18. The semiconductor device as claimed in claim 11 , wherein the gates of the first, second, third and fourth transistors are ring-shaped.
19. The semiconductor device as claimed in claim 12 , wherein the gates of the pair transistors are ring-shaped.